One-bit memory cell in static random access memory device with PMOS thin film transistor load pair

Claim 1

A semiconductor memory device for storing one-bit information in one of a plurality of memory cells, each memory cell including two transfer transistors, two driving transistors, and two load transistors, each load transistor comprising: a source formed of first and second semi-conductive layers with said second semi-conductive layer of said source being stacked on said first semi-conductive layer of said source, said source being connected to a constant power source line, said first and second semi-conductive layers being dissimilarly doped, said first semi-conductive layer being more heavily doped than said second semi-conductive layer; a drain spaced apart from said source and formed of said first and second semi-conductive layers with said second semi-conductive layer of said drain being stacked on said first semi-conductive layer of said drain, said drain being connected to another drain of a corresponding one of said driving transistors; a channel region formed substantially of said second semi-conductive layer, said second semi-conductive layer extending from said source through said channel region to said drain; and a gate formed over a gate insulating layer, said gate insulating layer being interposed between said gate and said channel region.