US5172203A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device with polycrystalline silicon active region and method of fabrication thereof
Assignee: Sony Corp
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Filing: 1987-09-11
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Granted: 1992-12-15
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Expires: 2007-09-11
Abstract
Abstract A polycrystalline silicon layer is used to allow simultaneous fabrication of both N- and P-type MOSFET's on a common channel layer during integrated circuit fabrication. The polysilicon layer is between 20 Å and 750 Å thick, and preferably between 200 Å and 500 Å thick. These dimensions afford the polysilicon layer the high effective mobility, low threshold voltage and low leakage current characteristics, especially if the vapor-deposited polysilicon layer is annealed and/or ion implanted with Si + or Ge + after deposition. Application of the polysilicon layer over adjoining insulating and P-type semicondcuting areas allows the single polysilicon layer to serve as active terminals and channels of both conductivity types of MOS transistors without intervening insulating or semiconducting layers. Deposition of the polysilicon layer in direct contact with a single-crystal substrate enhances the beneficial electrical properties of the polysilicon layer, especially if the polysilicon layer is annealed following deposition.
Inventors
- 👤 Hisao Hayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:40
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6731; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D62/00; H10D62/40; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D86/00; H10D86/201; H10D88/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
244 words
A IC chip comprising: a semiconductor substrate; an insulating layer formed on said substrate; a polycrystalline silicon layer formed over said substrate and said insulating layer, said polycrystalline silicon layer having a thickness in a range of 100Å to 750Å for obtaining high effective mobility; a first semiconductor device of a first conductivity type formed in said polycrystalline silicon layer; and a second semiconductor device of a second, opposing conductivity type formed in said polycrystalline silicon layer; wherein said first and second semiconductor devices are MOS transistors having respective source regions and drain regions in said polycrystalline layer; wherein said source region of said first semiconductor device abuts said drain region of said second semiconductor device; and wherein the IC chip is produced by a process comprising the steps of: forming said insulating layer which is deposited on said semiconductor substrate, the insulating layer leaving a section of said semiconductor substrate exposed; depositing said polycrystalline silicon layer over said insulating layer and over said exposed section of said semiconductor substrate; performing an ion implantation of an element from the same elemental family as silicon into said polycrystalline silicon layer; forming said MOS transistors in said polycrystalline silicon layer over said insulating layer and over said exposed section of said semiconductor substrate; and forming a bridging electrode over at least a portion of said source region of said first semiconductor device and at least a portion of said drain region of said second semiconductor device.
Claim 2
Dependent Claim
244 words
A IC chip comprising: a semiconductor substrate; an insulating layer formed on said substrate; a polycrystalline silicon layer formed over said substrate and said insulating layer, said polycrystalline silicon layer having a thickness in a range of 100Å to 750Å for obtaining high effective mobility; a first semiconductor device of a first conductivity type formed in said polycrystalline silicon layer; and a second semiconductor device of a second, opposing conductivity type formed in said polycrystalline silicon layer; wherein said first and second semiconductor devices are MOS transistors having respective source regions and drain regions in said polycrystalline layer; wherein said source region of said first semiconductor device abuts said drain region of said second semiconductor device; and wherein the IC chip is produced by a process comprising the steps of: forming said insulating layer which is deposited on said semiconductor substrate, the insulating layer leaving a section of said semiconductor substrate exposed; depositing said polycrystalline silicon layer over said insulating layer and over said exposed section of said semiconductor substrate; performing an ion implantation of an element from the same elemental family as silicon into said polycrystalline silicon layer; forming said MOS transistors in said polycrystalline silicon layer over said insulating layer and over said exposed section of said semiconductor substrate; and forming a bridging electrode over at least a portion of said source region of said first semiconductor device and at least a portion of said drain region of said second semiconductor device.
Claim 3
Dependent Claim
24 words
The IC chip as set forth in claim 1, in which a step of annealing said polycrystalline layer follows said step of ion implantation.
Claim 4
Dependent Claim
25 words
The IC chip as set forth in claim 1 wherein said MOS transistors are formed from common polycrystalline silicon, gate oxide and gate electrode layers.
Claim 5
Dependent Claim
233 words
An IC chip comprising: a semiconductor substrate; an insulating layer formed on said substrate; a polycrystalline silicon layer formed over said substrate and said insulating layer, said polycrystalline silicon layer having a thickness in a range of 100Å and 750Å for obtaining high effective mobility; a first semiconductor device of a first conductivity type formed in said polycrystalline silicon layer; and a second semiconductor device of a second, opposing conductivity type formed in said polycrystalline silicon layer; wherein said first and second semiconductor devices are MOS transistors having respective source regions and drain regions in said polycrystalline layer; wherein said source region of said first semiconductor device abuts said drain region of said second semiconductor device; and wherein the IC chip is produced by a process comprising the steps of: forming said insulating layer which is deposited on said semiconductor substrate, the insulating layer leaving a section of said semiconductor substrate exposed; depositing said polycrystalline silicon layer over said insulating layer and over said exposed section of said semiconductor substrate; performing an ion implantation of an element form the same elemental family as silicon into said polycrystalline silicon layer; forming said MOS transistors in said polycrystalline silicon layer over said insulating layer and over said exposed section of said semiconductor substrate; and forming electrodes such that MOS transistors are connected via a common input gate terminal and a common output drain electrode terminal.
Claim 6
Dependent Claim
233 words
An IC chip comprising: a semiconductor substrate; an insulating layer formed on said substrate; a polycrystalline silicon layer formed over said substrate and said insulating layer, said polycrystalline silicon layer having a thickness in a range of 100Å and 750Å for obtaining high effective mobility; a first semiconductor device of a first conductivity type formed in said polycrystalline silicon layer; and a second semiconductor device of a second, opposing conductivity type formed in said polycrystalline silicon layer; wherein said first and second semiconductor devices are MOS transistors having respective source regions and drain regions in said polycrystalline layer; wherein said source region of said first semiconductor device abuts said drain region of said second semiconductor device; and wherein the IC chip is produced by a process comprising the steps of: forming said insulating layer which is deposited on said semiconductor substrate, the insulating layer leaving a section of said semiconductor substrate exposed; depositing said polycrystalline silicon layer over said insulating layer and over said exposed section of said semiconductor substrate; performing an ion implantation of an element form the same elemental family as silicon into said polycrystalline silicon layer; forming said MOS transistors in said polycrystalline silicon layer over said insulating layer and over said exposed section of said semiconductor substrate; and forming electrodes such that MOS transistors are connected via a common input gate terminal and a common output drain electrode terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-15 | 1996-06-15 | 1996-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-15 | 2000-06-15 | 2000-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-15 | 2004-06-15 | 2004-12-15 | $7700.00 | Window Closed / Lapsed |