Semiconductor device having an improved thin film transistor

Claim 2

A semiconductor device comprising a semiconductor substrate of a first conductivity type; a first insulating layer formed on said semiconductor substrate; and a thin film field effect transistor formed on said semiconductor substrate via said first insulating layer, said thin film field effect transistor including a gate electrode formed on said first insulating layer, a second insulating layer covering an upper surface and first and second side surfaces of said gate electrode, and a semiconductor film formed on said semiconductor substrate via said first and second insulating layers and having a first region of a second conductivity type opposite to said first conductivity type, a second region of said first conductivity type formed in contact with a first end of said first region, and a third region of said first conductivity type and formed in contact with a second end of said first region, said gate electrode and a part of said first region being overlapped with each other via said second insulating layer, said second end of said first region being apart from said second side surface of said gate electrode by a distance more than a thickness of a part of said second inslutating layer covering said second side surface of said gate electrode and being not overlapped with said gate electrode, wherein said second and third regions serves as a source and a drain of said thin film field effect transistor, respectively.

Claim 3

The semiconductor device according to claim 1, in which said first end of said first region is apart from said first side surface of said gate electrode by a distance more than a thickness of a part of said second insulating layer covering said first side surface of said gate electrode and is not overlapped with said gate electrode.

Claim 4

The semiconductor device according to claim 1, in which said semiconductor film is formed of a polycrystalline silicon layer.

Claim 5

The semicoductor device according to claim 1, in which said gate electrode is formed of polycrystalline silicon.

Claim 6

The semiconductor device according to claim 1, in which said first conductivity type is a P type and said second conductivity type is an N type.

Claim 7

The semiconductor device according to claim 1, in which said first region extends from a first location of said second insulating layer above said upper surface of said gate electrode to a second location of said first insulating layer on a side of said second side surface of said gate electrode along a surface of the part of said second insulating layer covering said second side surface of said gate electrode.

Claim 8

The semiconductor device according to claim 1, in which said first region is located above said upper surface of said gate electrode above said upper surface of said gate electrode and on said second side surface of said gate electrode via said second insulating layer.

Claim 9

A semiconductor device comprising a semiconductor substrate of a first conductivity type, a first region of a second, conductivity type formed in said semiconductor substrate, a second region of said second conductivity type formed in said semiconductor substrate and being apart from said first region, a first insulating layer formed on a surface of said semiconductor substrate, a gate electrode formed on a part of the surface of said semiconductor substrate approximately between said first and second regions via said first insulating layer, a second insulating layer covering an upper surface and first and second side surfaces of said gate electrode, a semiconductor film formed on the surface of said gate electrode and said semiconductor substrate via said second and first insulating layers, said semiconductor film having a third region of said second conductivity type, a fourth region of said first conductivity type adjacent to a first end of said third region and a fifth region of said first conductivity type adjacent to a second end of said third region, a part of said third region being overlapped with said gate electrode, said second end of said third region being apart from said second side surface of said gate electrode by a distance more than a thickness of a part of said second insulating layer covering said second side surface and being not overlapped with said gate electrode, and means for electrically connecting said fifth region to said second region, wherein said first region and said second region serve as a source and a drain of a first field effect transistor of a first channel type and said fourth region and said fifth region service as a source and a drain of a second field effect transistor of a second channel type opposite to said first channel type.

Claim 10

A semiconductor device comprising a semiconductor substrate of a first conductivity type, a first region of a second, conductivity type formed in said semiconductor substrate, a second region of said second conductivity type formed in said semiconductor substrate and being apart from said first region, a first insulating layer formed on a surface of said semiconductor substrate, a gate electrode formed on a part of the surface of said semiconductor substrate approximately between said first and second regions via said first insulating layer, a second insulating layer covering an upper surface and first and second side surfaces of said gate electrode, a semiconductor film formed on the surface of said gate electrode and said semiconductor substrate via said second and first insulating layers, said semiconductor film having a third region of said second conductivity type, a fourth region of said first conductivity type adjacent to a first end of said third region and a fifth region of said first conductivity type adjacent to a second end of said third region, a part of said third region being overlapped with said gate electrode, said second end of said third region being apart from said second side surface of said gate electrode by a distance more than a thickness of a part of said second insulating layer covering said second side surface and being not overlapped with said gate electrode, and means for electrically connecting said fifth region to said second region, wherein said first region and said second region serve as a source and a drain of a first field effect transistor of a first channel type and said fourth region and said fifth region service as a source and a drain of a second field effect transistor of a second channel type opposite to said first channel type.

Claim 11

The semiconductor device according to claim 8, in which said first end of said third region is apart from said first side surface of said gate electrode by a distance more than a thickness of a part of said second insulating layer covering said first side surface of said gate electrode and is not overlapped with said gate electrode.

Claim 12

The semiconductor device according to claim 8, in which said semiconductor film is formed of polycrystalline silicon.

Claim 13

The semiconductor device according to claim 8, in which said third region extends from a first location above said upper surface of said gate electrode to a second location above said second region along said second side surface of said gate electrode via said second insulating layer.

Claim 14

A semiconductor device including a plurality of static memory cells formed in a semiconductor substrate of a first conductivity type, each of said static memory cells comprising a flip-flop circuit including first and second inverters, input terminals of said first and second inverters being connected to output terminals of said second and first inverters, respectively, each of said first and second inverters including a first insulated gate field effect transistor of a first channel type and a second insulated gate field effect transitor of a second channel type opposite to said first channel type, said first transistor having first and second separate regions formed in said substrate, a first insulating layer formed on a surface of said substrate and a conductive layer formed on a part of the surface of said substrate between said first and second regions, said second transistor having a second insulating layer covering an upper surface and first and second side surfaces of said conductive layer, a semiconductor film formed on said conductive layer and said substrate via said second and first insulating layers, said semiconductor layer having a third region of said second conductivity type, a fourth region of said first conductivity type adjacent to a first end of said third region and a fifth region of said first conductivity type adjacent to a second end of said third region, a part of said third region being overlapped with said conductive layer, said second end of said third region being apart from said second side surface of said conductive layer by a distance more than a thickness of a part of said second insulating layer covering said second side surface and not overlapped with said conductive layer, wherein said fifth region and said fourth region serve as a drain and a source of said second transistor, respectively and said conductive layer serves as gates of said first and second transistors.

Claim 15

A semiconductor device including a plurality of static memory cells formed in a semiconductor substrate of a first conductivity type, each of said static memory cells comprising a flip-flop circuit including first and second inverters, input terminals of said first and second inverters being connected to output terminals of said second and first inverters, respectively, each of said first and second inverters including a first insulated gate field effect transistor of a first channel type and a second insulated gate field effect transitor of a second channel type opposite to said first channel type, said first transistor having first and second separate regions formed in said substrate, a first insulating layer formed on a surface of said substrate and a conductive layer formed on a part of the surface of said substrate between said first and second regions, said second transistor having a second insulating layer covering an upper surface and first and second side surfaces of said conductive layer, a semiconductor film formed on said conductive layer and said substrate via said second and first insulating layers, said semiconductor layer having a third region of said second conductivity type, a fourth region of said first conductivity type adjacent to a first end of said third region and a fifth region of said first conductivity type adjacent to a second end of said third region, a part of said third region being overlapped with said conductive layer, said second end of said third region being apart from said second side surface of said conductive layer by a distance more than a thickness of a part of said second insulating layer covering said second side surface and not overlapped with said conductive layer, wherein said fifth region and said fourth region serve as a drain and a source of said second transistor, respectively and said conductive layer serves as gates of said first and second transistors.

Claim 16

The semiconductor device according to claim 12, in which said first end of said third region is apart from said first side surface of said conductive layer by a distance more than a thickness of a part of said second insulating layer covering said first side surface of said conductive layer and is not overlapped with said conductive layer.

Claim 17

The semiconductor device according to claim 12, in which said semiconductor film is formed of polycrystalline silicon.

Claim 18

The semiconductor device according to claim 12, in which said third region extends from a first location above said upper surface of said gate electrode to a second location above said second region along said second side surface of said gate electrode via said second insulating layer.