Patent JPS62165884A successfully refreshed from Google Patents.
US5592013A
Expired / Lapsed
US
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Semiconductor device and method of fabricating the same
Assignee: Mitsubishi Electric Corp
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Filing: 1995-06-06
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Granted: 1997-01-07
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Expires: 2015-06-06
Abstract
Abstract In a semiconductor memory device, an n-well is formed in the memory cell area on the surface of a p-type semiconductor substrate. A p-well is formed on the surface of the n-well, and a memory cell transistor is formed on the surface of the p-well. Another p-well is formed in the peripheral circuit area on the substrate surface, and a peripheral transistor is formed on the surface of the p-well. The p-wells are connected electrically by a conductor layer so that these regions have the same voltage level. The memory cell transistor has its threshold voltage set higher than that of the peripheral transistor. The memory device consumes less power, has less decay of gate oxide film, and is suitable for high-density integration.
Inventors
- 👤 Hiroki Honda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 03:03
CPC Classifications
H; H10; H10B; H10B10/00; H10B10/12; H10B10/125; H10B10/18; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0181; H10D84/0188; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/853; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
281 words
A semiconductor memory device having a memory cell area including static-type memory cells, and a peripheral circuit area, said device comprising: a semiconductor substrate of a first conductivity type having a major surface; a first impurity region of a second conductivity type formed within said memory cell area at the major surface of said semiconductor substrate; a second impurity region of the first conductivity type which is formed within said first impurity region at the major surface of said semiconductor substrate and includes impurity of the first conductivity type at a first concentration at a position near the major surface of said semiconductor substrate; first MIS transistors each having a pair of source/drain regions formed by being spaced out from each other by a prescribed distance within said second impurity region at the major surface of said semiconductor substrate, and a gate electrode layer formed on the area between said source/drain regions by being interposed with a gate insulating layer; a third impurity region of the first conductivity type which is formed within said peripheral circuit area at the major surface of said semiconductor substrate and includes impurity of the first conductivity type at a second concentration which is lower than said first concentration at a position near the major surface of said semiconductor substrate; and a second MIS transistor having a pair of source/drain regions formed by being spaced out from each other by a prescribed distance within said third impurity region at the major surface of said semiconductor substrate, and a gate electrode layer formed on the area between said source/drain regions by being interposed with a gate insulating layer, said second and third impurity regions being connected electrically.
Claim 2
Dependent Claim
281 words
A semiconductor memory device having a memory cell area including static-type memory cells, and a peripheral circuit area, said device comprising: a semiconductor substrate of a first conductivity type having a major surface; a first impurity region of a second conductivity type formed within said memory cell area at the major surface of said semiconductor substrate; a second impurity region of the first conductivity type which is formed within said first impurity region at the major surface of said semiconductor substrate and includes impurity of the first conductivity type at a first concentration at a position near the major surface of said semiconductor substrate; first MIS transistors each having a pair of source/drain regions formed by being spaced out from each other by a prescribed distance within said second impurity region at the major surface of said semiconductor substrate, and a gate electrode layer formed on the area between said source/drain regions by being interposed with a gate insulating layer; a third impurity region of the first conductivity type which is formed within said peripheral circuit area at the major surface of said semiconductor substrate and includes impurity of the first conductivity type at a second concentration which is lower than said first concentration at a position near the major surface of said semiconductor substrate; and a second MIS transistor having a pair of source/drain regions formed by being spaced out from each other by a prescribed distance within said third impurity region at the major surface of said semiconductor substrate, and a gate electrode layer formed on the area between said source/drain regions by being interposed with a gate insulating layer, said second and third impurity regions being connected electrically.
Claim 3
Dependent Claim
60 words
A semiconductor memory device according to claim 1, wherein said first MIS transistors include an access transistor and driver transistor which constitute said memory cell, the threshold voltage of said driver transistor being higher than the threshold voltage of said access transistor, the threshold voltage of said access transistor being higher than the threshold voltage of said second MIS transistor.
Claim 4
Dependent Claim
49 words
A semiconductor memory device according to claim 2, wherein said driver transistor has a threshold voltage of 0.65 V or higher, said access transistor has a threshold voltage of 0.50 V or higher and below 0.65 V, and said second MIS transistor has a threshold voltage below 0.50 V.
Claim 5
Dependent Claim
113 words
A semiconductor memory device according to claim 3, wherein impurity of the first conductivity type in the area between the source/drain regions of said driver transistor has a concentration of 2.4×10 16 cm -3 or more at a position near the major substrate surface, impurity of the first conductivity type in the area between the source/drain regions of said access transistor has a concentration of 1.8×10 16 cm 3 or more and below 2.4×10 16 cm -3 at a position near the major substrate surface, and impurity of the second conductivity type in the area between the source/drain regions of said second MIS transistor has a concentration below 1.8×10 16 cm -3 .
Claim 6
Dependent Claim
55 words
A semiconductor memory device according to claim 1 further including: an insulating layer which is formed on said first and second MIS transistors and has holes which reach the surface of said second and third impurity regions; and a conductive layer which connects said second and third impurity regions electrically by way of said holes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |