Method for fabricating polycide gate MOSFET devices

Claim 1

A method for fabricating metal oxide semiconductor field effect transistor device on a semiconductor substrate, comprising the steps of: forming a gate electrode structure on said semiconductor substrate which structure includes a gate oxide layer, a polysilicon gate layer, and a refractory metal silicide layer; forming a first thin thermal oxide layer over the exposed surfaces of said gate electrode structure and said semiconductor substrate, said refractory metal silicide layer being transformed from its amorphous form into a crystalline form; forming lightly doped source/drain regions in said semiconductor substrate by a first ion implantation procedure using said gate electrode structure as a mask; forming a dielectric layer over said first thin thermal oxide layer; anisotropically etching said dielectric layer and said first thin thermal oxide layer to form sidewall spacers on the side walls of said gate electrode structure; transforming said refractory metal silicide layer from its crystalline form into its amorphous form by a second ion implantation procedure; forming a second thin thermal oxide layer over the exposed surfaces of said gate electrode structure, and said semiconductor substrate; and forming heavily doped source/drain regions in said semiconductor substrate by a third ion implantation procedure using said gate electrode structure and said sidewall spacers as a mask.

Claim 2

A method for fabricating metal oxide semiconductor field effect transistor device on a semiconductor substrate, comprising the steps of: forming a gate electrode structure on said semiconductor substrate which structure includes a gate oxide layer, a polysilicon gate layer, and a refractory metal silicide layer; forming a first thin thermal oxide layer over the exposed surfaces of said gate electrode structure and said semiconductor substrate, said refractory metal silicide layer being transformed from its amorphous form into a crystalline form; forming lightly doped source/drain regions in said semiconductor substrate by a first ion implantation procedure using said gate electrode structure as a mask; forming a dielectric layer over said first thin thermal oxide layer; anisotropically etching said dielectric layer and said first thin thermal oxide layer to form sidewall spacers on the side walls of said gate electrode structure; transforming said refractory metal silicide layer from its crystalline form into its amorphous form by a second ion implantation procedure; forming a second thin thermal oxide layer over the exposed surfaces of said gate electrode structure, and said semiconductor substrate; and forming heavily doped source/drain regions in said semiconductor substrate by a third ion implantation procedure using said gate electrode structure and said sidewall spacers as a mask.