Patent US5472896A successfully refreshed from Google Patents.
US5472896A
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US
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Method for fabricating polycide gate MOSFET devices
Assignee: United Microelectronics Corp
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Filing: 1994-11-14
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Granted: 1995-12-05
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Expires: 2014-11-14
Abstract
Abstract A method of fabricating MOSFET device with polycide gate, which includes a polysilicon layer and a refractory metal silicide layer, is described. After a thin oxide layer is formed by a thermal process, the refractory metal silicide layer is transformed from an amorphous form to a crystalline form that leads to peeling and surface roughness problems in the prior art. This method utilizes an additional ion implantation step to transform the refractory metal silicide layer from the crystalline form back into the amorphous form. Hence, the problems of peeling and surface roughness of the polycide gate can be overcome.
Inventors
- 👤 Anchor Chen
- 👤 Gary Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 11:44
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D64/021
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
207 words
A method for fabricating metal oxide semiconductor field effect transistor device on a semiconductor substrate, comprising the steps of: forming a gate electrode structure on said semiconductor substrate which structure includes a gate oxide layer, a polysilicon gate layer, and a refractory metal silicide layer; forming a first thin thermal oxide layer over the exposed surfaces of said gate electrode structure and said semiconductor substrate, said refractory metal silicide layer being transformed from its amorphous form into a crystalline form; forming lightly doped source/drain regions in said semiconductor substrate by a first ion implantation procedure using said gate electrode structure as a mask; forming a dielectric layer over said first thin thermal oxide layer; anisotropically etching said dielectric layer and said first thin thermal oxide layer to form sidewall spacers on the side walls of said gate electrode structure; transforming said refractory metal silicide layer from its crystalline form into its amorphous form by a second ion implantation procedure; forming a second thin thermal oxide layer over the exposed surfaces of said gate electrode structure, and said semiconductor substrate; and forming heavily doped source/drain regions in said semiconductor substrate by a third ion implantation procedure using said gate electrode structure and said sidewall spacers as a mask.
Claim 2
Independent Claim
207 words
A method for fabricating metal oxide semiconductor field effect transistor device on a semiconductor substrate, comprising the steps of: forming a gate electrode structure on said semiconductor substrate which structure includes a gate oxide layer, a polysilicon gate layer, and a refractory metal silicide layer; forming a first thin thermal oxide layer over the exposed surfaces of said gate electrode structure and said semiconductor substrate, said refractory metal silicide layer being transformed from its amorphous form into a crystalline form; forming lightly doped source/drain regions in said semiconductor substrate by a first ion implantation procedure using said gate electrode structure as a mask; forming a dielectric layer over said first thin thermal oxide layer; anisotropically etching said dielectric layer and said first thin thermal oxide layer to form sidewall spacers on the side walls of said gate electrode structure; transforming said refractory metal silicide layer from its crystalline form into its amorphous form by a second ion implantation procedure; forming a second thin thermal oxide layer over the exposed surfaces of said gate electrode structure, and said semiconductor substrate; and forming heavily doped source/drain regions in said semiconductor substrate by a third ion implantation procedure using said gate electrode structure and said sidewall spacers as a mask.
Claim 3
Dependent Claim
23 words
The method for fabricating metal oxide semiconductor field effect transistor device of claim 1, wherein said refractory metal silicide layer comprises tungsten silicide.
Claim 4
Dependent Claim
24 words
The method for fabricating metal oxide semiconductor field effect transistor device of claim 1, wherein said second ion implantation is performed using arsenic ions.
Claim 5
Dependent Claim
23 words
The method for fabricating metal oxide semiconductor field effect transistor device of claim 1, wherein said second ion implantation is performed using argon.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-12-04 | 1999-06-05 | 1999-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-12-04 | 2003-06-05 | 2003-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-12-04 | 2007-06-05 | 2007-12-05 | $7700.00 | Window Closed / Lapsed |