US5340761A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned contacts with gate overlapped lightly doped drain (goldd) structure
Assignee: Philips Semiconductors Inc
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Filing: 1991-10-31
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Granted: 1994-08-23
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Expires: 2011-10-31
Abstract
Abstract In a method for producing a transistor with an overlapping gate region, a gate region is placed on a substrate between two source/drain regions. Spacers are placed around the gate region. The spacers are formed of dielectric material. A thin layer of polysilicon is deposited over the two source/drain regions and over electrically insulating regions adjacent to the two source/drain regions. Portions of the thin layer of polysilicon are oxidized to electrically isolate the two source/drain regions. A metal-silicide layer is formed on the portions of the thin layer of polysilicon which are not oxidized. The metal-silicide layer is connected to a metal layer. The electrical contact of the metal-silicide layer and the metal layer is over an electrically insulating layer.
Inventors
- 👤 Ying T. Loh
- 👤 Chung S. Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:37
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/021
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
159 words
A method for producing a transistor with an overlapping gate region, the method comprising the steps of: (a) placing on a substrate between two source/drain regions, a gate region which includes a polysilicon region, the gate region being placed on top of a dielectric region; the polysilicon region being used as part of a gate region; (b) forming spacers around the gate region, the spacers being composed of dielectric material; and, (c) forming a thin layer of polysilicon over the two source/drain regions and over electrically insulating regions adjacent to the two source/drain regions; (d) oxidizing portions of the thin layer of polysilicon to electrically isolate the two source/drain regions; (e) forming a metal-silicide layer on the portions of the thin layer of polysilicon which are not oxidized; and, (f) connecting the metal-silicide layer to a metal layer through a contact hole, an electrical contact of the metal-silicide layer and the metal layer being over the electrically insulating layer.
Claim 2
Independent Claim
159 words
A method for producing a transistor with an overlapping gate region, the method comprising the steps of: (a) placing on a substrate between two source/drain regions, a gate region which includes a polysilicon region, the gate region being placed on top of a dielectric region; the polysilicon region being used as part of a gate region; (b) forming spacers around the gate region, the spacers being composed of dielectric material; and, (c) forming a thin layer of polysilicon over the two source/drain regions and over electrically insulating regions adjacent to the two source/drain regions; (d) oxidizing portions of the thin layer of polysilicon to electrically isolate the two source/drain regions; (e) forming a metal-silicide layer on the portions of the thin layer of polysilicon which are not oxidized; and, (f) connecting the metal-silicide layer to a metal layer through a contact hole, an electrical contact of the metal-silicide layer and the metal layer being over the electrically insulating layer.
Claim 3
Dependent Claim
64 words
A method as in claim 1 wherein step (a) includes the following substeps: (a.1) depositing a first polysilicon layer; (a.2) forming a metal-silicide layer over the polysilicon layer; (a.3) forming an oxide on top of the metal-silicide layer; and, (a.4) masking and etching the first polysilicon layer, the metal-silicide layer and the oxide on top of the metal-silicide layer to form the gate region.
Claim 4
Dependent Claim
28 words
A method as in claim 1 wherein before step (b), the following step is performed: (g) implanting atoms of a first conductivity type into the two source/drain regions.
Claim 5
Dependent Claim
14 words
A method as in claim 3 wherein the first conductivity type is n-type conductivity.
Claim 6
Dependent Claim
29 words
A method as in claim 3 wherein before step (d) the following step is performed: (h) implanting atoms of a first conductivity type into the thin layer of polysilicon.
Claim 7
Dependent Claim
16 words
A method as in claim 5 wherein in step (h) n + -type atoms are implanted.
Claim 8
Dependent Claim
55 words
A method as in claim 1 wherein step (d) includes the substeps of: (d.1) depositing a layer of nitride; (d.2) patterning and etching the layer of nitride to expose portions of the thin layer of polysilicon; (d.3) oxidizing the exposed portions of the thin layer of polysilicon; and, (d.4) stripping away the layer of nitride.
Claim 9
Dependent Claim
60 words
A method as in claim 1 wherein step (e) comprises the substeps of: (e.1) depositing a metal layer; (e.2) performing a rapid thermal anneal on the metal layer deposited in step (e.1) to form the metal-silicide layer over the portions of the thin layer of polysilicon which are not oxidized; and, (e.3) stripping off unreacted portions of the metal layer.
Claim 10
Dependent Claim
15 words
A method as in claim 8 wherein the metal in the metal layer is titanium.
Claim 11
Dependent Claim
21 words
A method as in claim 1 wherein before step (c) residual gate oxide over the two source/drain regions is dipped off.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |