Peeling free metal silicide films using rapid thermal anneal

Claim 1

The method for fabricating a lightly doped source/drain MOS FET integrated circuit device with a peeling-free metal silicide gate electrode comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer, and metal silicide layer; annealing said gate oxide, said polysilicon layer and said metal silicide layer using a rapid thermal annealing process at a temperature more than about 1000° C. and for a time of between about 30 to 60 seconds; forming a pattern of lightly doped regions in said substrate by ion implantation using said structures as the mask; blanket depositing a dielectric layer over the surfaces of the structure at a temperature of between about 650° to 750° C.; etching the said blanket layer to form a dielectric spacer structure upon the sidewalls of each of said gate electrode structures and over the adjacent portions of said substrate, and to remove the said dielectric layer from the top surfaces of said metal silicide layer; driving in said pattern of lightly doped regions by rapid thermal annealing at a temperature of more than about 1000° C. and for a time of between about 30 to 60 seconds with said metal silicide layer having no covering thereover; forming heavily doped regions in said substrate by ion implantation using the said gate electrode structures with spacer structures as the mask to produce said lightly doped drain under said spacer structure of an MOS FET device; and forming a passivation layer over the said structures and electrical connecting structures thereover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device.

Claim 2

The method for fabricating a lightly doped source/drain MOS FET integrated circuit device with a peeling-free metal silicide gate electrode comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer, and metal silicide layer; annealing said gate oxide, said polysilicon layer and said metal silicide layer using a rapid thermal annealing process at a temperature more than about 1000° C. and for a time of between about 30 to 60 seconds; forming a pattern of lightly doped regions in said substrate by ion implantation using said structures as the mask; blanket depositing a dielectric layer over the surfaces of the structure at a temperature of between about 650° to 750° C.; etching the said blanket layer to form a dielectric spacer structure upon the sidewalls of each of said gate electrode structures and over the adjacent portions of said substrate, and to remove the said dielectric layer from the top surfaces of said metal silicide layer; driving in said pattern of lightly doped regions by rapid thermal annealing at a temperature of more than about 1000° C. and for a time of between about 30 to 60 seconds with said metal silicide layer having no covering thereover; forming heavily doped regions in said substrate by ion implantation using the said gate electrode structures with spacer structures as the mask to produce said lightly doped drain under said spacer structure of an MOS FET device; and forming a passivation layer over the said structures and electrical connecting structures thereover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device.

Claim 13

The method for fabricating a lightly doped source/drain MOS FET integrated circuit device having a peeling-free metal silicide gate electrode comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer, and a tungsten silicide; annealing said gate oxide, said polysilicon layer and said metal silicide gate electrode using a rapid thermal annealing process at a temperature more than about 1000° C. and for a time of less than 60 seconds; forming a pattern of lightly doped regions in said substrate by ion implantation using said structures as the mask; blanket depositing a dielectric layer over the surfaces of the structure at a temperature of between about 650° to 750° C.; etching the said blanket layer to form a dielectric spacer structure upon the sidewalls of each of said gate electrode structures and over the adjacent portions of said substrate, and removing said dielectric from the top surface of said silicide layer; driving in said pattern of lightly doped regions by rapid thermal annealing at a temperature of more than about 1000° C. and for a time of less than about 60 seconds with said metal silicide having no covering thereover; forming heavily doped regions in said substrate by ion implantation using the said gate electrode structures with spacer structures as the mask to produce said lightly doped drain under said spacer structures of an MOS FET device; and forming a passivation layer over the said structures and electrical connecting structures thereover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device.

Claim 14

The method for fabricating a lightly doped source/drain MOS FET integrated circuit device having a peeling-free metal silicide gate electrode comprising: forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer, and a tungsten silicide; annealing said gate oxide, said polysilicon layer and said metal silicide gate electrode using a rapid thermal annealing process at a temperature more than about 1000° C. and for a time of less than 60 seconds; forming a pattern of lightly doped regions in said substrate by ion implantation using said structures as the mask; blanket depositing a dielectric layer over the surfaces of the structure at a temperature of between about 650° to 750° C.; etching the said blanket layer to form a dielectric spacer structure upon the sidewalls of each of said gate electrode structures and over the adjacent portions of said substrate, and removing said dielectric from the top surface of said silicide layer; driving in said pattern of lightly doped regions by rapid thermal annealing at a temperature of more than about 1000° C. and for a time of less than about 60 seconds with said metal silicide having no covering thereover; forming heavily doped regions in said substrate by ion implantation using the said gate electrode structures with spacer structures as the mask to produce said lightly doped drain under said spacer structures of an MOS FET device; and forming a passivation layer over the said structures and electrical connecting structures thereover to electrically connect the said gate electrode structures and source/drain elements to form said integrated circuit device.