US5206187A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of processing semiconductor wafers using a contact etch stop
Assignee: Micron Technology Inc
•
Filing: 1991-12-17
•
Granted: 1993-04-27
•
Expires: 2011-12-17
Abstract
Abstract A method of processing a semiconductor wafer comprises: a) fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations of the wafer; b) providing a layer of transition metal oxide elevationally above the active regions; c) applying an insulating dielectric layer elevationally above the transition metal oxide layer; d) etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and e) etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.
Inventors
- 👤 Trung T. Doan
- 👤 Gurtej S. Sandhu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 06:28
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P50/283; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/081; Y; Y10; Y10S; Y10S148/00; Y10S148/019; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
269 words
A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductively doped silicon containing active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer; depositing a layer of transition metal atop the wafer which contacts the surfaces of the active regions and other areas on the wafer; the transition metal layer having a thickness, an outer region and an inner region; processing the wafer under conditions which reacts a) the transition metal of the inner region over the silicon containing active regions with such silicon to produce a transition metal silicide, and b) the transition metal of the outer region to form a transition metal oxide thereby transforming the outer region over the other areas into transition metal oxide and the transition metal over the silicon containing active regions into sandwich regions of outer transition metal oxide and adjacent transition metal silicide in contact with the active regions; the outer transition metal oxide regions of the sandwich regions having outer surfaces positioned at varying elevations on the wafer; applying an insulating dielectric layer atop the wafer; selectively etching the insulating dielectric layer over selected portions of different elevation sandwich regions using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch in etching of the insulating dielectric layer in a single etch step to selected outer surfaces of the sandwich regions which are at different elevations; and etching the transition metal oxide from the selected portions of outer transition metal sandwich regions.
Claim 2
Independent Claim
269 words
A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductively doped silicon containing active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer; depositing a layer of transition metal atop the wafer which contacts the surfaces of the active regions and other areas on the wafer; the transition metal layer having a thickness, an outer region and an inner region; processing the wafer under conditions which reacts a) the transition metal of the inner region over the silicon containing active regions with such silicon to produce a transition metal silicide, and b) the transition metal of the outer region to form a transition metal oxide thereby transforming the outer region over the other areas into transition metal oxide and the transition metal over the silicon containing active regions into sandwich regions of outer transition metal oxide and adjacent transition metal silicide in contact with the active regions; the outer transition metal oxide regions of the sandwich regions having outer surfaces positioned at varying elevations on the wafer; applying an insulating dielectric layer atop the wafer; selectively etching the insulating dielectric layer over selected portions of different elevation sandwich regions using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch in etching of the insulating dielectric layer in a single etch step to selected outer surfaces of the sandwich regions which are at different elevations; and etching the transition metal oxide from the selected portions of outer transition metal sandwich regions.
Claim 3
Dependent Claim
33 words
The method of processing a semiconductor wafer of claim 1 wherein the transition metal is selected from the group consisting of Ti, Mo, Ta, Co, Pt, Pd, Ni and W, or alloys thereof.
Claim 4
Dependent Claim
28 words
The method of processing a semiconductor wafer of claim 1 wherein the transition metal is applied to a thickness of from about 200 Angstroms to about 600 Angstroms.
Claim 5
Dependent Claim
23 words
The method of processing a semiconductor wafer of claim 3 wherein the transition metal is applied to a thickness of about 300 Angstroms.
Claim 6
Dependent Claim
51 words
The method of processing a semiconductor wafer of claim 1 wherein, the transition metal is selected from the group consisting of Ti, Mo, Ta, Co, Pt, Pd, Ni and W, or alloys thereof; and the transition metal is applied to a thickness of from about 200 Angstroms to about 600 Angstroms.
Claim 7
Dependent Claim
27 words
The method of processing a semiconductor wafer of claim 1 wherein the step of processing the wafer comprises heating the wafer in an oxidizing atmosphere containing oxygen.
Claim 8
Dependent Claim
21 words
The method of processing a semiconductor wafer of claim 6 wherein the step of processing the wafer comprises rapid thermal processing.
Claim 9
Dependent Claim
115 words
The method of processing a semiconductor wafer of claim 1 wherein the plurality of conductively doped active regions comprises sources and drains of field effect transistors, the field effect transistors having gates; the method further comprising depositing an insulating dielectric layer atop the wafer over the field effect transistor gates before deposition of the transition metal, the insulating dielectric deposited over the field effect transistor gates being selected such the transition metal oxide is selectively etchable relative to such insulating dielectric, and wherein the step of etching the transition metal oxide comprises etching the transition metal oxide with a chemistry which is selective relative to the insulating dielectric deposited over the field effect transistor gates.
Claim 10
Independent Claim
287 words
A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductively doped silicon containing active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer; depositing a layer of elemental titanium metal atop the wafer which contacts the surfaces of the active regions and other areas on the wafer; the titanium layer having a thickness, an outer region and an inner region; processing the wafer under conditions which reacts a) the titanium of the inner region over the silicon containing active regions with such silicon to produce a titanium silicide comprising a formula TiSi x , where "x" is from about 1.0 to 2.5, and b) the titanium of the outer region to form a titanium oxide comprising a formula TiO y , where "y" is from about 1.0 to 2.0 thereby transforming the outer region over the other areas into TiO y and the titanium over the silicon containing active regions into sandwich regions of outer TiO y and adjacent TiSi x in contact with the active regions; the outer TiO y regions of the sandwich regions having outer surfaces positioned at varying elevations on the wafer; applying an insulating dielectric layer atop the wafer; selectively etching the insulating dielectric layer over selected portions of different elevation sandwich regions using an etch chemistry which is highly selective to the TiO y and using the TiO y as an effective etch stop in etching of the insulating dielectric layer in a single etch step to selected outer surfaces of the sandwich regions which are at different elevations; and etching the TiO y from the selected portions of outer regions of the sandwich regions.
Claim 11
Independent Claim
287 words
A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductively doped silicon containing active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer; depositing a layer of elemental titanium metal atop the wafer which contacts the surfaces of the active regions and other areas on the wafer; the titanium layer having a thickness, an outer region and an inner region; processing the wafer under conditions which reacts a) the titanium of the inner region over the silicon containing active regions with such silicon to produce a titanium silicide comprising a formula TiSi x , where "x" is from about 1.0 to 2.5, and b) the titanium of the outer region to form a titanium oxide comprising a formula TiO y , where "y" is from about 1.0 to 2.0 thereby transforming the outer region over the other areas into TiO y and the titanium over the silicon containing active regions into sandwich regions of outer TiO y and adjacent TiSi x in contact with the active regions; the outer TiO y regions of the sandwich regions having outer surfaces positioned at varying elevations on the wafer; applying an insulating dielectric layer atop the wafer; selectively etching the insulating dielectric layer over selected portions of different elevation sandwich regions using an etch chemistry which is highly selective to the TiO y and using the TiO y as an effective etch stop in etching of the insulating dielectric layer in a single etch step to selected outer surfaces of the sandwich regions which are at different elevations; and etching the TiO y from the selected portions of outer regions of the sandwich regions.
Claim 12
Dependent Claim
27 words
The method of processing a semiconductor wafer of claim 9 wherein the titanium is applied to a thickness of from about 200 Angstroms to about 600 Angstroms.
Claim 13
Dependent Claim
22 words
The method of processing a semiconductor wafer of claim 10 wherein the titanium is applied to a thickness of about 300 Angstroms.
Claim 14
Dependent Claim
27 words
The method of processing a semiconductor wafer of claim 9 wherein the step of processing the wafer comprises heating the wafer in an oxidizing atmosphere containing oxygen.
Claim 15
Dependent Claim
21 words
The method of processing a semiconductor wafer of claim 9 wherein the step of processing the wafer comprises rapid thermal processing.
Claim 16
Dependent Claim
35 words
The method of processing a semiconductor wafer of claim 9 wherein the step of selectively etching the insulating dielectric is conducted with an etchant gas chemistry comprising CHF 3 , Ar, and CF 4 .
Claim 17
Dependent Claim
40 words
The method of processing a semiconductor wafer of claim 9 further comprising etching the TiO y from the selected portions of outer regions of the sandwich regions with a solution of NH 4 OH or H 2 SO 4 .
Claim 18
Dependent Claim
66 words
The method of processing a semiconductor wafer of claim 9 wherein, the step of selectively etching the insulating dielectric is conducted with an etchant gas chemistry comprising CHF 3 , Ar, and CF 4 ; and further comprising: etching the TiO y from the selected portions of outer regions of the sandwich regions with a solution of NH 4 OH or H 2 SO 4 .
Claim 19
Dependent Claim
27 words
The method of processing a semiconductor wafer of claim 16 wherein the titanium is applied to a thickness of from about 200 Angstroms to about 600 Angstroms.
Claim 20
Dependent Claim
27 words
The method of processing a semiconductor wafer of claim 16 wherein the step of processing the wafer comprises heating the wafer in an oxidizing atmosphere containing oxygen.
Claim 21
Dependent Claim
113 words
The method of processing a semiconductor wafer of claim 9 wherein the plurality of conductively doped active regions comprises sources and drains of field effect transistors, the field effect transistors having gates; the method further comprising depositing an insulating dielectric layer atop the wafer over the field effect transistor gates before deposition of the TiO y , the insulating dielectric deposited over the field effect transistor gates being selected such the TiO y is selectively etchable relative to such insulating dielectric, and wherein the step of etching the TiO y comprises etching the TiO y with a chemistry which is selective relative to the insulating dielectric deposited over the field effect transistor gates.
Claim 22
Independent Claim
202 words
A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductively doped silicon containing active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer; converting the outwardly exposed surfaces of the active regions into a barrier transition metal silicide which connects with the active regions; providing a layer of transition metal oxide over the barrier transition metal silicide of the active regions thereby producing sandwich regions of outer transition metal oxide regions and adjacent transition metal silicide in contact with the active regions; the outer transition metal oxide regions of the sandwich regions having outer surfaces positioned at varying elevations on the wafer; applying an insulating dielectric layer atop the wafer; selectively etching the insulating dielectric layer over selected portions of different elevation sandwich regions using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop in etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and etching the transition metal oxide from the selected portions of outer transition metal sandwich regions.
Claim 23
Independent Claim
202 words
A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductively doped silicon containing active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer; converting the outwardly exposed surfaces of the active regions into a barrier transition metal silicide which connects with the active regions; providing a layer of transition metal oxide over the barrier transition metal silicide of the active regions thereby producing sandwich regions of outer transition metal oxide regions and adjacent transition metal silicide in contact with the active regions; the outer transition metal oxide regions of the sandwich regions having outer surfaces positioned at varying elevations on the wafer; applying an insulating dielectric layer atop the wafer; selectively etching the insulating dielectric layer over selected portions of different elevation sandwich regions using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop in etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and etching the transition metal oxide from the selected portions of outer transition metal sandwich regions.
Claim 24
Dependent Claim
47 words
The method of processing a semiconductor wafer of claim 20 wherein the transition metal of the barrier metal silicide and the transition metal of the transition metal oxide are selected from the group consisting of Ti, Mo, Ta, Co, Pt, Pd, Ni, and W, or alloys thereof.
Claim 25
Dependent Claim
21 words
The method of processing a semiconductor wafer of claim 20 wherein the transition metal of the barrier metal silicide comprises titanium.
Claim 26
Dependent Claim
21 words
The method of processing a semiconductor wafer of claim 20 wherein the transition metal of the transition metal oxide comprises titanium.
Claim 27
Dependent Claim
32 words
The method of processing a semiconductor wafer of claim 20 wherein the transition metal of the barrier metal silicide and the transition metal of the transition metal oxide consists essentially of titanium.
Claim 28
Dependent Claim
88 words
The method of processing a semiconductor wafer of claim 20 wherein the step of converting comprises: depositing a layer of transition metal atop the wafer over the outwardly exposed active region surfaces; heating the wafer to react the transition metal over the outwardly exposed active regions with the underlying silicon to produce the transition metal silicide; etching unreacted transition metal from the wafer; and wherein the step of providing a layer of transition metal oxide over the barrier transition metal silicide comprises depositing a layer transition metal oxide.
Claim 29
Dependent Claim
47 words
The method of processing a semiconductor wafer of claim 25 wherein the transition metal of the barrier metal silicide and the transition metal of the transition metal oxide are selected from the group consisting of Ti, Mo, Ta, Co, Pt, Pd, Ni and W, or alloys thereof.
Claim 30
Dependent Claim
21 words
The method of processing a semiconductor wafer of claim 25 wherein the transition metal of the barrier metal silicide comprises titanium.
Claim 31
Dependent Claim
21 words
The method of processing a semiconductor wafer of claim 25 wherein the transition metal of the transition metal oxide comprises titanium.
Claim 32
Dependent Claim
31 words
The method processing a semiconductor wafer of claim 25 wherein the transition metal of the barrier metal silicide and the transition metal of the transition metal oxide consists essentially of titanium.
Claim 33
Dependent Claim
116 words
The method of processing a semiconductor wafer of claim 20 wherein the plurality of conductively doped active regions comprises sources and drains of field effect transistors, the field effect transistors having gates; the method further comprising depositing an insulating dielectric layer atop the wafer over the field effect transistor gates before deposition of the transition metal oxide, the insulating dielectric deposited over the field effect transistor gates being selected such the transition metal oxide is selectively etchable relative to such insulating dielectric, and wherein the step of etching the transition metal oxide comprises etching the transition metal oxide with a chemistry which is selective relative to the insulating dielectric deposited over the field effect transistor gates.
Claim 34
Independent Claim
162 words
A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer: providing a layer of transition metal oxide elevationally above the active regions: providing a barrier layer of insulating dielectric atop the wafer and over the active regions before providing the layer of transition metal oxide atop the wafer; applying an insulating dielectric layer elevationally above the transition metal oxide layer; etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.
Claim 35
Independent Claim
162 words
A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer: providing a layer of transition metal oxide elevationally above the active regions: providing a barrier layer of insulating dielectric atop the wafer and over the active regions before providing the layer of transition metal oxide atop the wafer; applying an insulating dielectric layer elevationally above the transition metal oxide layer; etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.
Claim 36
Dependent Claim
26 words
The method of processing a semiconductor wafer of claim 31 wherein the insulating dielectric barrier layer is provided to a thickness of at least 500 Angstroms.
Claim 37
Dependent Claim
47 words
The method of processing a semiconductor wafer of claim 31 wherein the barrier layer of insulating dielectric is provided to a thickness of at least 500 Angstroms; and wherein, the transition metal oxide is provided to a thickness of from about 200 Angstroms to about 4000 Angstroms.
Claim 38
Independent Claim
180 words
A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer: providing a layer of transition metal oxide comprising a titanium oxide comprising a formula TiO y , where "y" is from about 1.0 to 2.0 elevationally above the active regions: providing a barrier layer of insulating dielectric atop the wafer and over the active regions before providing the layer of transition metal oxide atop the wafer; applying an insulating dielectric layer elevationally above the transition metal oxide layer; etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.
Claim 39
Independent Claim
180 words
A method of processing a semiconductor wafer comprising the following steps: fabricating a wafer to define a plurality of conductively doped active regions, the active regions having outwardly exposed surfaces positioned at varying elevations on the wafer: providing a layer of transition metal oxide comprising a titanium oxide comprising a formula TiO y , where "y" is from about 1.0 to 2.0 elevationally above the active regions: providing a barrier layer of insulating dielectric atop the wafer and over the active regions before providing the layer of transition metal oxide atop the wafer; applying an insulating dielectric layer elevationally above the transition metal oxide layer; etching selected portions of the insulating dielectric layer over different elevation active areas using an etch chemistry which is highly selective to the transition metal oxide and using the transition metal oxide as an effective etch stop enabling etching of the insulating dielectric layer in a single etch step to adjacent selected active regions which are at different elevations; and etching the transition metal oxide from the selected portions and upwardly exposing selected active regions.
Claim 40
Dependent Claim
26 words
The method of processing a semiconductor wafer of claim 34 wherein the insulating dielectric barrier layer is provided to a thickness of at least 500 Angstroms.
Claim 41
Dependent Claim
49 words
The method of processing a semiconductor wafer of claim 34 wherein the barrier layer of insulating dielectric is provided to a thickness of at least 500 Angstroms or greater; and wherein, the transition metal oxide is provided to a thickness of from about 200 Angstroms to about 4000 Angstroms.
References Cited (Backward Citations)
US4593454A
Cited
US4665608A
Cited
US4657628A
Cited
US4767724A
Cited
US4795722A
Cited
US4881105A
Cited
US5026666A
Cited
US5022958A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-26 | 1996-10-26 | 1997-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-26 | 2000-10-26 | 2001-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-26 | 2004-10-26 | 2005-04-27 | $7700.00 | Window Closed / Lapsed |