US5837568A
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US
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Manufacturing method of semiconductor devices
Assignee: Sanyo Electric Co Ltd
•
Filing: 1996-12-10
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Granted: 1998-11-17
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Expires: 2016-12-10
Abstract
Abstract To provide a manufacturing method of thin film transistors (TFT) using poly-silicone and having an LDD structure. In particular, the LDD sections of the TFTs are formed in an improved method so as to achieve a high throughput and stable performance of the TFTs. To be specific, the LD region is doped at a low concentration in the ion implantation method which includes mass spectrometry because high controllability over a dose is required. On the other hand, the source and drain regions are doped at a higher concentration than the LD region in the ion showering method which does not include mass spectrometry. Using the ion showering method, poly-crystal silicon can be doped such that less doping damage is caused thereto. This makes it possible to apply a lower temperature for annealing, such as RTA, to activate doped impurities so as to prevent the substrate from being curved. Further, combination of the ion implantation method and the showering method achieves a high throughput production of TFTs having stable performance.
Inventors
- 👤 Kiyoshi Yoneda
- 👤 Yoshihiro Morimoto
- 👤 Kiichi Hirano
- 👤 Koji Suzuki
- 👤 Masaru Takeuchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:03
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0321; H10D30/6704; H10D30/6713; H10D30/6715; H10P; H10P32/00; H10P32/10; H10P32/12; H10P32/1204
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
171 words
A manufacturing method of a semiconductor device, comprising: a first step of forming a low concentration region by doping a given region of a semiconductor layer with a small dose of first impurities which cause a conductive type; and a second step of forming a high concentration region by doping a given region which is at least partially different from the low concentration region with a large dose of second impurities which cause a same conductive type as the first impurities; wherein, in the first step, ions of the first impurities are selected through mass spectrometry from ions which have been extracted from material source containing elements of the first impurities through electrical discharging and application of a high electric field thereto, and doped in the semiconductor layer, and in the second step, ions of the second impurities are extracted together with other ions from material source containing elements of the second impurities through electrical discharging and application of a high electric field thereto, and all doped in the semiconductor layer.
Claim 2
Dependent Claim
171 words
A manufacturing method of a semiconductor device, comprising: a first step of forming a low concentration region by doping a given region of a semiconductor layer with a small dose of first impurities which cause a conductive type; and a second step of forming a high concentration region by doping a given region which is at least partially different from the low concentration region with a large dose of second impurities which cause a same conductive type as the first impurities; wherein, in the first step, ions of the first impurities are selected through mass spectrometry from ions which have been extracted from material source containing elements of the first impurities through electrical discharging and application of a high electric field thereto, and doped in the semiconductor layer, and in the second step, ions of the second impurities are extracted together with other ions from material source containing elements of the second impurities through electrical discharging and application of a high electric field thereto, and all doped in the semiconductor layer.
Claim 3
Dependent Claim
39 words
A manufacturing method of a semiconductor device as defined in claim 1, wherein the material source containing elements of the second impurities is a gaseous mixture consisting of hydrogen and hydrogen compound of the elements of the second impurities.
Claim 4
Dependent Claim
30 words
A manufacturing method of a semiconductor device as defined in claim 2, wherein the ions of the second impurities are doped with a dose 1×10 14 cm -2 or more.
Claim 5
Dependent Claim
209 words
A manufacturing method of a semiconductor device, comprising: a first step of forming a low concentration region by doping a given region of a semiconductor layer with a small dose of first impurities which cause a conductive type; a second step of forming a high concentration region by doping a given region which is at least partially different from the low concentration region with a large dose of second impurities which cause a same conductive type as the first impurities; and a third step of annealing the low and high concentration regions formed in the semiconductor layer for activation of impurities therein; wherein, in the first step, ions of the first impurities are selected through mass spectrometry from ions which have been extracted from material containing elements of the first impurities through electrical discharging and application of a high electric field thereto, and doped in the semiconductor layer, in the second step, ions of the second impurities are extracted together with other ions from material containing elements of the second impurities through electrical discharging and application of a high electric field thereto, and all doped in the semiconductor layer, and in the third step, the semiconductor layer is scanned by an approaching heat source at a given relative speed.
Claim 6
Dependent Claim
209 words
A manufacturing method of a semiconductor device, comprising: a first step of forming a low concentration region by doping a given region of a semiconductor layer with a small dose of first impurities which cause a conductive type; a second step of forming a high concentration region by doping a given region which is at least partially different from the low concentration region with a large dose of second impurities which cause a same conductive type as the first impurities; and a third step of annealing the low and high concentration regions formed in the semiconductor layer for activation of impurities therein; wherein, in the first step, ions of the first impurities are selected through mass spectrometry from ions which have been extracted from material containing elements of the first impurities through electrical discharging and application of a high electric field thereto, and doped in the semiconductor layer, in the second step, ions of the second impurities are extracted together with other ions from material containing elements of the second impurities through electrical discharging and application of a high electric field thereto, and all doped in the semiconductor layer, and in the third step, the semiconductor layer is scanned by an approaching heat source at a given relative speed.
Claim 7
Dependent Claim
38 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the material containing elements of the second impurities is a gaseous mixture consisting of hydrogen and hydrogen compound of the elements of the second impurities.
Claim 8
Dependent Claim
32 words
A manufacturing method of a semiconductor device as defined in claim 5, wherein the semiconductor layer is scanned by the heat source at a relative scanning speed of 10 mm/sec or over.
Claim 9
Dependent Claim
30 words
A manufacturing method of a semiconductor device as defined in claim 5, wherein the ions of the second impurities are doped with a dose 1×10 14 cm -2 or more.
Claim 10
Dependent Claim
26 words
A manufacturing method of a semiconductor device as defined in claim 5, wherein the semiconductor is scanned by the heat source at 600° C. or over.
Claim 11
Dependent Claim
32 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the semiconductor layer is scanned by the heat source at a relative scanning speed of 10 mm/sec or over.
Claim 12
Dependent Claim
32 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the semiconductor layer is scanned by the heat source at a relative scanning speed of 12 mm/sec or over.
Claim 13
Dependent Claim
30 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the ions of the second impurities are doped with a dose 1×10 14 cm -2 or more.
Claim 14
Dependent Claim
30 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the ions of the second impurities are doped with a dose 7×10 14 cm -2 or more.
Claim 15
Dependent Claim
30 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the ions of the second impurities are doped with a dose 3×10 15 cm -2 or more.
Claim 16
Dependent Claim
27 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the semiconductor layer is scanned by the heat source at 600° C. or over.
Claim 17
Dependent Claim
27 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the semiconductor layer is scanned by the heat source at 780° C. or over.
Claim 18
Dependent Claim
50 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the semiconductor layer is scanned by the heat source at a relative scanning speed of 12 mm/sec or over, and the ions of the second impurities are doped with a dose 7×10 14 cm -2 or more.
Claim 19
Dependent Claim
37 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the semiconductor layer is scanned by the heat source at 780° C. or over at a relative scanning speed of 12 mm/sec or over.
Claim 20
Dependent Claim
55 words
A manufacturing method of a semiconductor device as defined in claim 4, wherein the ions of the second impurities are doped with a dose 7×10 14 cm -2 or more, and the semiconductor layer is scanned by the heat source at 780° C. or over at a relative scanning speed of 12 mm/sec or over.
Claim 21
Dependent Claim
229 words
A manufacturing method of thin film transistors formed on one of a pair of substrates having liquid crystal display interposed therebetween and altogether constituting a liquid crystal display, thin film transistors for driving the liquid crystal for every pixel and thin film transistors for driving the thin film transistors for driving the liquid crystal, comprising: a step of forming a semiconductor layer on the substrate, a step of forming a low concentration area by doping a given region of the semiconductor layer with a small dose of ions of first impurities which cause a conductive type, in which the ions of the first impurities are selected through mass spectrometry from ions which have been extracted from material containing elements of the first impurities through electrical discharging and a high electrical field thereto, and a step of forming a high concentration area partially adjacent to the low concentration region by doping a given region which is at least partially different from the low concentration region in the semiconductor layer with a large dose of ions of second impurities which cause the same conductive type as the first impurities, in which the ions of the second impurities are extracted together with other ions through electrical discharging and application of a high electric field thereto, and all doped into the part of the low concentration region to form the high concentration region.
Claim 22
Dependent Claim
229 words
A manufacturing method of thin film transistors formed on one of a pair of substrates having liquid crystal display interposed therebetween and altogether constituting a liquid crystal display, thin film transistors for driving the liquid crystal for every pixel and thin film transistors for driving the thin film transistors for driving the liquid crystal, comprising: a step of forming a semiconductor layer on the substrate, a step of forming a low concentration area by doping a given region of the semiconductor layer with a small dose of ions of first impurities which cause a conductive type, in which the ions of the first impurities are selected through mass spectrometry from ions which have been extracted from material containing elements of the first impurities through electrical discharging and a high electrical field thereto, and a step of forming a high concentration area partially adjacent to the low concentration region by doping a given region which is at least partially different from the low concentration region in the semiconductor layer with a large dose of ions of second impurities which cause the same conductive type as the first impurities, in which the ions of the second impurities are extracted together with other ions through electrical discharging and application of a high electric field thereto, and all doped into the part of the low concentration region to form the high concentration region.
Claim 23
Dependent Claim
45 words
A manufacturing method of a thin film transistor as defined in claim 19, further comprising a step of annealing the semiconductor layer by scanning with an approaching heat source at a given relative speed for activation of impurities in the low and high concentration regions.
Claim 24
Dependent Claim
50 words
A manufacturing method of a thin film transistor as defined in claim 20, wherein the semiconductor layer is scanned by the heat source at a relative speed of 12 mm/sec or over, and the ions of the second impurities are doped with a dose 7×10 14 cm -2 or more.
Claim 25
Dependent Claim
38 words
A manufacturing method of a thin film transistor as defined in claim 20, wherein the semiconductor layer is scanned by the heat source at 780° C. or over at a relative scanning speed of 12 mm/sec or over.
Claim 26
Dependent Claim
56 words
A manufacturing method of a thin film transistor as defined in claim 20, wherein the semiconductor layer is scanned by the heat source at 780° C. or over at a relative scanning speed of 12 mm/sec or over, and the ions of the second impurities are doped with a dose 7×10 14 cm -2 or more.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-11-16 | 2002-05-18 | 2002-11-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-11-16 | 2006-05-18 | 2006-11-17 | $3760.00 | Window Closed / Lapsed |
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