← Back to Patent Explorer
US5767558A Expired / Lapsed US ⏱️ 0.0 years remaining

Structures for preventing gate oxide degradation

Assignee: Renesas Electronics America Inc
•
Filing: 1996-05-10
•
Granted: 1998-06-16
•
Expires: 2016-05-10
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract The degradation of integrity of the gate oxide in a CMOS transistor due to the formation of a tungsten silicide strapping layer on the polycrystalline silicon gate as a result of the migration of fluorine atoms from the tungsten hexafluoride used to form the tungsten silicide is reduced by increasing the dopant concentration of the polycrystalline silicon layer thereby to form dopant atoms in the grain boundaries of the polycrystalline silicon to block the migration of fluorine through the polycrystalline silicon to the underlying gate oxide. By preventing fluorine from reaching the gate oxide in this manner, the degradation of the gate oxide due to the replacement of oxygen by fluorine is decreased. The method maintains the gate-oxide integrity (such as charge-to-breakdown characteristics), and the method also makes more predictable the performance of the resulting transistors by reducing the thickening of the oxide due to the migration of oxygen replaced by fluorine into the underlying silicon substrate thereby to form additional silicon oxide. The polysilicon thus preserves the gate oxide integrity. In addition, the heavily-doped polysilicon will also sufficiently dope the contacted polysilicon and thus reduce the contact resistance of the polycrystalline silicon and silicon.

Inventors

  • 👤 Guo-Qiang (Patrick) Lo
  • 👤 Shih-Ked Lee

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 21:05
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/01312; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 88 words
A semiconductor device comprising: a gate oxide layer overlying a semiconductor substrate, such that the oxide layer is substantially free of fluorine atoms; and a doped polycrystalline silicon layer overlying said gate oxide layer and underlying a metal silicide layer, said polycrystalline layer directly contacting said metal silicide layer, and said polycrystalline silicon being doped to a dopant concentration of at least approximately 10 21 atoms/cm 3 to substantially block the passage of atoms from said metal silicide layer above said polycrystalline silicon layer and through the polycrystalline.
Claim 2
Dependent Claim 88 words
A semiconductor device comprising: a gate oxide layer overlying a semiconductor substrate, such that the oxide layer is substantially free of fluorine atoms; and a doped polycrystalline silicon layer overlying said gate oxide layer and underlying a metal silicide layer, said polycrystalline layer directly contacting said metal silicide layer, and said polycrystalline silicon being doped to a dopant concentration of at least approximately 10 21 atoms/cm 3 to substantially block the passage of atoms from said metal silicide layer above said polycrystalline silicon layer and through the polycrystalline.
Claim 3
Dependent Claim 21 words
The device of claim 1 wherein the concentration of fluorine atoms in said gate oxide layer is approximately 10 18 atoms/cc.
Claim 4
Dependent Claim 18 words
The device of claim 1 wherein said gate-oxide region has a width of approximately 60 to 200 Å.
Claim 5
Dependent Claim 12 words
The device of claim 1 wherein said metal silicide is tungsten silicide.
Claim 6
Dependent Claim 20 words
The device of claim 4 wherein the ratio of W atoms to Si atoms is 1: approximately 2.5 to 2.8.
Claim 7
Dependent Claim 18 words
A semiconductor device as in claim 1 wherein said doped polycrystalline silicon layer substantially reduces gate oxide degradation.
Claim 8
Dependent Claim 99 words
A semiconductor device comprising: a gate oxide layer overlying a semiconductor substrate, the oxide layer being substantially free of fluorine atoms; a first polycrystalline silicon layer overlying said gate oxide layer, said first polycrystalline silicon layer being doped to a dopant concentration of at least approximately 10 21 atoms/cm 3 to substantially block the passage of atoms from a metal silicide layer above said polycrystalline silicon layer; and a second doped polycrystalline silicon layer overlying said first polycrystalline layer and underlying a metal silicide layer, said second doped polycrystalline layer being less highly doped than said first polycrystalline layer.
Claim 9
Dependent Claim 99 words
A semiconductor device comprising: a gate oxide layer overlying a semiconductor substrate, the oxide layer being substantially free of fluorine atoms; a first polycrystalline silicon layer overlying said gate oxide layer, said first polycrystalline silicon layer being doped to a dopant concentration of at least approximately 10 21 atoms/cm 3 to substantially block the passage of atoms from a metal silicide layer above said polycrystalline silicon layer; and a second doped polycrystalline silicon layer overlying said first polycrystalline layer and underlying a metal silicide layer, said second doped polycrystalline layer being less highly doped than said first polycrystalline layer.
Claim 10
Dependent Claim 21 words
The device of claim 7 wherein the concentration of fluorine atoms in said gate oxide layer is approximately 10 18 atoms/cc.
Claim 11
Dependent Claim 18 words
The device of claim 7 wherein said gate-oxide region has a width of approximately 60 to 200 Å.
Claim 12
Dependent Claim 21 words
The device of claim 7 wherein said second layer of doped polycrystalline silicon has a concentration of approximately 10 20 atoms/cc.
Claim 13
Dependent Claim 18 words
The device of claim 7 wherein said metal silicide is tungsten silicide formed using a compound including fluorine.
Claim 14
Dependent Claim 20 words
The device of claim 11 wherein the ratio of W atoms to Si atoms is 1: approximately 2.5 to 2.8.
Claim 15
Dependent Claim 19 words
A semiconductor device as in claim 7 wherein said doped first polycrystalline silicon layer substantially reduces gate oxide degradation.

References Cited (Backward Citations)

US5256894A Cited
US5214305A Cited
US5364803A Cited
US5371396A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-06-15 2001-12-15 2002-06-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-06-15 2005-12-15 2006-06-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-06-15 2009-12-15 2010-06-16 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag