Structure for flash memory cell

Claim 2

A self-aligned flash memory MOS field effect transistor device comprising: a silicon semiconductor substrate having an upper surface, a source region and a drain region formed in said substrate on said upper surface, a tunnel oxide structure formed over the surface of said substrate including said surface over said source and said drain regions, said tunnel oxide structure including only two layers comprising a thermal oxide layer having a thickness between about 50Å and about 100Å formed upon said substrate and a film of silicon rich oxide having a thickness between about 50Å and about 200Å formed upon said thermal oxide layer, and a gate structure composed of a stack formed upon said silicon rich oxide film, said stack comprising a floating gate electrode, a dielectric layer formed upon said floating gate layer and a control electrode polysilicon layer formed upon said dielectric layer, said floating gate electrode of said gate structure including a lower portion composed of relatively smaller grain size crystals with substantial asperities and having a thickness between about 300Å and about 600Å, and an upper portion having a thickness between about 1,000Å and about 2,000Å of having a smoother surface than said lower portion, said lower portion of said floating gate electrode of said gate structure comprising a polysilicon structure formed by LPCVD at a temperature of about 630° C. and said upper portion of said floating gate electrode comprising silicon with a large grain size and a smooth surface.

Claim 3

A transistor structure in accordance with claim 1 wherein a native polyoxide is provided as a boundary between said lower portion and said upper portion of said floating gate electrode, whereby there is provided a good interrupting material for grain growth and a good conducting interface between silicon layers.

Claim 4

A self-aligned flash memory MOS field effect transistor device comprising: a silicon semiconductor substrate having an upper surface, a source region and a drain region formed in said substrate on said upper surface, a tunnel oxide structure formed over the surface of said substrate including said surface over said source and said drain regions, said tunnel oxide structure including only two layers comprising a thermal oxide layer having a thickness between about 50Å and about 100Å formed upon said substrate and a film of silicon rich oxide having a thickness between about 50Å and about 200Å formed upon said thermal oxide layer, and a gate structure composed of a stack formed upon said silicon rich oxide film, said stack comprising a floating gate electrode, a dielectric layer formed upon said floating gate layer and a control electrode polysilicon layer formed upon said dielectric layer, said floating gate electrode of said gate structure including a lower portion composed of relatively smaller grain size crystals with substantial asperities and having a thickness between about 300Å and about 600Å, and an upper portion with larger grain size crystals having a thickness between about 1,000Å and about 2,000Å of polysilicon having a smoother surface than said lower portion, whereby flash memory erasing speed is enhanced with concomitant increased tunnel oxide thickness.

Claim 5

A self-aligned flash memory MOS field effect transistor device comprising: a silicon semiconductor substrate having an upper surface, a source region and a drain region formed in said substrate on said upper surface, a tunnel oxide structure formed over the surface of said substrate including said surface over said source and said drain regions, said tunnel oxide structure including only two layers comprising a thermal oxide layer having a thickness between about 50Å and about 100Å formed upon said substrate and a film of silicon rich oxide having a thickness between about 50Å and about 200Å formed upon said thermal oxide layer, and a gate structure composed of a stack formed upon said silicon rich oxide film, said stack comprising a floating gate electrode, a dielectric layer formed upon said floating gate layer and a control electrode polysilicon layer formed upon said dielectric layer, said floating gate electrode of said gate structure including a lower portion composed of relatively smaller grain size crystals with substantial asperities and having a thickness between about 300Å and about 600Å, and an upper portion with larger grain size crystals having a thickness between about 1,000Å and about 2,000Å of polysilicon having a smoother surface than said lower portion, whereby flash memory erasing speed is enhanced with concomitant increased tunnel oxide thickness.

Claim 6

A self-aligned flash memory MOS field effect transistor structure comprising: a) a silicon semiconductor substrate having an upper surface, b) a source region and a drain region formed in said substrate on said upper surface, c) a tunnel oxide structure deposited over the surface of said substrate including said surface over said source and said drain regions, d) said tunnel oxide structure including only two layers comprising a thermal oxide layer formed upon said substrate and a film of silicon rich oxide formed upon said thermal oxide layer, said tunnel oxide structure including a thermal oxide layer having a thickness between about 50Å and about 100Å formed upon said substrate and a film of silicon rich oxide having a thickness between about 50Å and about 200Å formed upon said thermal oxide layer, and e) a gate structure composed of a stack formed upon said silicon rich oxide film, said stack comprising a first polysilicon layer, a dielectric layer formed upon said polysilicon layer and a second polysilicon layer formed upon said dielectric layer, said first polysilicon layer of said gate structure including a lower portion composed of relatively smaller grain size crystals with asperities, and an upper portion composed of polysilicon having a smoother surface than said lower portion, said first polysilicon layer having a thickness between about 300Å and about 600Å, and said upper portion having larger grain size crystals with a thickness between about 1,000Å and about 2,000Å of polysilicon having a smoother surface than said lower portion, whereby flash memory erasing speed is enhanced with concomitant increased tunnel oxide thickness.

Claim 7

A self-aligned flash memory MOS field effect transistor structure comprising: a) a silicon semiconductor substrate having an upper surface, b) a source region and a drain region formed in said substrate on said upper surface, c) a tunnel oxide structure deposited over the surface of said substrate including said surface over said source and said drain regions, d) said tunnel oxide structure including only two layers comprising a thermal oxide layer formed upon said substrate and a film of silicon rich oxide formed upon said thermal oxide layer, said tunnel oxide structure including a thermal oxide layer having a thickness between about 50Å and about 100Å formed upon said substrate and a film of silicon rich oxide having a thickness between about 50Å and about 200Å formed upon said thermal oxide layer, and e) a gate structure composed of a stack formed upon said silicon rich oxide film, said stack comprising a first polysilicon layer, a dielectric layer formed upon said polysilicon layer and a second polysilicon layer formed upon said dielectric layer, said first polysilicon layer of said gate structure including a lower portion composed of relatively smaller grain size crystals with asperities, and an upper portion composed of polysilicon having a smoother surface than said lower portion, said first polysilicon layer having a thickness between about 300Å and about 600Å, and said upper portion having larger grain size crystals with a thickness between about 1,000Å and about 2,000Å of polysilicon having a smoother surface than said lower portion, whereby flash memory erasing speed is enhanced with concomitant increased tunnel oxide thickness.

Claim 8

A transistor structure in accordance with claim 1 wherein said lower portion is lightly doped with impurities which result in a smaller grain size of polysilicon with a considerable quantity of said asperities, whereby abundant grain boundaries and asperities enhance the electric field and consequently enhance the erasing speed.

Claim 9

A transistor structure in accordance with claim 1 wherein said dielectric layer comprises oxide-nitride oxide.

Claim 10

A transistor structure in accordance with claim 6 wherein said oxide-nitride-oxide is formed by thin thermal oxide layer of about 80Å followed by a layer of nitride formed by LPCVD of about 100Å and final oxide layer between about 20Å and about 50Å.