US4748133A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Deposition of amorphous silicon for the formation of interlevel dielectrics in semiconductor memory devices
Assignee: NXP USA Inc
•
Filing: 1987-06-26
•
Granted: 1988-05-31
•
Expires: 2007-06-26
Abstract
Abstract A new and improved method using the deposition of amorphous silicon for the formation of semiconductor memory device interlevel dielectrics. After the deposition of a first polysilicon layer, an amorphous silicon layer is deposited thereon. The polysilicon layer and amorphous silicon layer are etched to form a floating gate. The amorphous silicon layer allows for the growth of thermal oxide layers to take place at lower temperatures thereby decreasing the temperature at which the oxide layers are grown while still repressing the asperity formation. This allows for high quality oxide insulation layers.
Inventors
- 👤 Mark D. Griswold
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 23:51
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10D30/60; H10D30/68; H10D30/6891; H10D64/00; H10D64/01; H10D64/031; H10D64/035; H10P14/40; H10P14/416
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
132 words
Method of making a semiconductor memory device comprising the steps of: providing a silicon wafer; isolating an area on said silicon wafer and defining a well thereon; growing a first oxide layer on said well; depositing a first polysilicon layer on said silicon wafer including said well and said first oxide layer; doping said first polysilicon layer; depositing an amorphous silicon layer on said doped polysilicon layer; defining and etching said first oxide layer, said doped polysilicon layer and said amorphous silicon layer to form a floating gate in said well; implanting a source and a drain; growing a second oxide layer on said well including said floating gate; depositing a second polysilicon layer on said second oxide layer; doping said second polysilicon layer; and defining and etching said doped second layer.
Claim 2
Dependent Claim
132 words
Method of making a semiconductor memory device comprising the steps of: providing a silicon wafer; isolating an area on said silicon wafer and defining a well thereon; growing a first oxide layer on said well; depositing a first polysilicon layer on said silicon wafer including said well and said first oxide layer; doping said first polysilicon layer; depositing an amorphous silicon layer on said doped polysilicon layer; defining and etching said first oxide layer, said doped polysilicon layer and said amorphous silicon layer to form a floating gate in said well; implanting a source and a drain; growing a second oxide layer on said well including said floating gate; depositing a second polysilicon layer on said second oxide layer; doping said second polysilicon layer; and defining and etching said doped second layer.
Claim 3
Dependent Claim
25 words
The method of claim 1 wherein the growing a first oxide layer step includes growing a first oxide layer having a thickness of 10 nanometers.
Claim 4
Dependent Claim
30 words
The method of claim 1 wherein the growing a first oxide layer step includes growing a first oxide layer having a thickness in the range of 5 to 15 nanometers.
Claim 5
Dependent Claim
25 words
The method of claim 1 wherein the growing a second oxide layer step includes growing a second oxide layer having a thickness of 40 nanometers.
Claim 6
Dependent Claim
30 words
The method of claim 1 wherein the growing a second oxide layer step includes growing a second oxide layer having a thickness in the range of 30 to 50 nanometers.
Claim 7
Dependent Claim
27 words
The method of claim 1 wherein the growing a second oxide layer step is performed at a temperature in the range of 1000 to 1050 degrees centigrade.
Claim 8
Dependent Claim
27 words
The method of claim 1 wherein the growing a second oxide layer step is performed at a temperature in the range of 950 to 1100 degrees centigrade.
Claim 9
Dependent Claim
21 words
The method of claim 1 wherein the steps of doping the first and second polysilicon layers include using a phosphorous dopant.
Claim 10
Dependent Claim
14 words
The method of claim 1 wherein the implanting step includes using a self-aligned implant.
Claim 11
Dependent Claim
20 words
The method of claim 1 wherein said method is performed a multiple number of times in a single silicon wafer.
Claim 12
Independent Claim
173 words
A method of making a semiconductor memory device comprising the steps of: providing a silicon wafer; isolating an area on said silicon wafer to provide a well; growing a first oxide layer on said well, said first oxide layer having a thickness in the range of 5 to 15 nanometers; depositing a first polysilicon layer on said silicon wafer including said well and said first oxide layer; doping said first polysilicon layer using a phosphorous dopant; depositing an amorphous silicon layer on said doped first polysilicon layer; defining and etching said doped first polysilicon layer and said amorphous silicon layer to form a floating gate in said well; implanting a source and a drain using a self-aligned implant; growing a second oxide layer on said well including said floating gate, said second oxide layer having a thickness in the range of 30 to 50 nanometers; depositing a second polysilicon layer on said second oxide layer; doping said second polysilicon layer using a phosphorous dopant; and defining and etching said doped second polysilicon layer.
Claim 13
Independent Claim
173 words
A method of making a semiconductor memory device comprising the steps of: providing a silicon wafer; isolating an area on said silicon wafer to provide a well; growing a first oxide layer on said well, said first oxide layer having a thickness in the range of 5 to 15 nanometers; depositing a first polysilicon layer on said silicon wafer including said well and said first oxide layer; doping said first polysilicon layer using a phosphorous dopant; depositing an amorphous silicon layer on said doped first polysilicon layer; defining and etching said doped first polysilicon layer and said amorphous silicon layer to form a floating gate in said well; implanting a source and a drain using a self-aligned implant; growing a second oxide layer on said well including said floating gate, said second oxide layer having a thickness in the range of 30 to 50 nanometers; depositing a second polysilicon layer on said second oxide layer; doping said second polysilicon layer using a phosphorous dopant; and defining and etching said doped second polysilicon layer.
Claim 14
Dependent Claim
19 words
The method of claim 11 wherein said method is performed a multiple number of times on a single wafer.
Claim 15
Independent Claim
64 words
A method of making a semiconductor memory device having an interlevel dielectric wherein a first oxide layer is grown on a silicon wafer, a polysilicon layer is formed on said first oxide layer, an amorphous silicon layer is formed on said first polysilicon layer and a second oxide layer is grown on said amorphous silicon layer, said second oxide layer providing said interlevel dielectric.
Claim 16
Independent Claim
64 words
A method of making a semiconductor memory device having an interlevel dielectric wherein a first oxide layer is grown on a silicon wafer, a polysilicon layer is formed on said first oxide layer, an amorphous silicon layer is formed on said first polysilicon layer and a second oxide layer is grown on said amorphous silicon layer, said second oxide layer providing said interlevel dielectric.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-05-31 | 1991-11-30 | 1992-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-05-31 | 1995-11-30 | 1996-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-05-31 | 1999-11-30 | 2000-05-31 | $7700.00 | Window Closed / Lapsed |