US4370798A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon
Assignee: Texas Instruments Inc
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Filing: 1981-07-20
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Granted: 1983-02-01
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Expires: 2001-07-20
Abstract
Abstract Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The second-level polysilicon is insulated from first-level polysilicon by multi-layer insulation; first, a thermal oxide layer provides better edge breakdown characteristics for transistors, then secondly a layer of doped deposited oxide provides improved step coverage, and finally an undoped deposited oxide is used to prevent out diffusion from doped oxide to second level polysilicon which would change the characteristics of the resistors.
Inventors
- 👤 Jih-Chang Lien
- 👤 Te-Long Chiu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:31
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10D88/00; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10W; H10W20/00; H10W20/01; H10W20/40; H10W20/45; H10W20/48
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
181 words
A method of making resistor elements in semiconductor integrated circuits, comprising the steps of: (a) depositing a first level of polycrystalline silicon over the face of a semiconductor body and patterning it to define electrodes of circuit elements on said face and interconnections between electrodes, (b) forming a triple-level insulator over said first level of polycrystalline silicon, the first level insulator being thermally grown silicon oxide on said first level of polycrystalline silicon, the second level insulator being doped low-temperature deposited silicon oxide densified for smooth step transistors, the third level insulator being undoped low-temperature deposited silicon oxide which acts as a diffusion barrier between the second level insulator and lightly doped resistors in second level polycrystalline silicon, (c) depositing a second level of polycrystalline silicon on said face and patterning it, the second level partially overlying the first level and overlying some of the circuit elements, (d) implanting conductivity-determining impurity material into the second level of polycrystalline silicon to provide resistor regions, (e) introducing conductivity-determining impurity material into selected areas of the second level of polycrystalline silicon to provide connections.
Claim 2
Independent Claim
181 words
A method of making resistor elements in semiconductor integrated circuits, comprising the steps of: (a) depositing a first level of polycrystalline silicon over the face of a semiconductor body and patterning it to define electrodes of circuit elements on said face and interconnections between electrodes, (b) forming a triple-level insulator over said first level of polycrystalline silicon, the first level insulator being thermally grown silicon oxide on said first level of polycrystalline silicon, the second level insulator being doped low-temperature deposited silicon oxide densified for smooth step transistors, the third level insulator being undoped low-temperature deposited silicon oxide which acts as a diffusion barrier between the second level insulator and lightly doped resistors in second level polycrystalline silicon, (c) depositing a second level of polycrystalline silicon on said face and patterning it, the second level partially overlying the first level and overlying some of the circuit elements, (d) implanting conductivity-determining impurity material into the second level of polycrystalline silicon to provide resistor regions, (e) introducing conductivity-determining impurity material into selected areas of the second level of polycrystalline silicon to provide connections.
Claim 3
Dependent Claim
18 words
A method according to claim 1 wherein the first level of polycrystalline silicon forms gates of MOS transistors.
Claim 4
Dependent Claim
26 words
A method according to claim 2 wherein the thickness of the first level insulator is much less than that of the second and third level insulators.
Claim 5
Dependent Claim
16 words
A method according to claim 2 wherein the step of introducing impurity material includes phosphorus diffusion.
Claim 6
Dependent Claim
26 words
A method according to claim 1 wherein a thin silicon oxide coating is applied over the resistor regions of the polycrystalline silicon after implanting impurity material.
Claim 7
Dependent Claim
21 words
A method according to claim 5 wherein the coating over the polycrystalline silicon functions to mask the introduction of impurity material.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-01-31 | 1986-08-02 | 1987-02-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-01-31 | 1990-08-02 | 1991-02-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-01-31 | 1994-08-02 | 1995-02-01 | $7700.00 | Window Closed / Lapsed |