US4291328A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interlevel insulator for integrated circuit with implanted resistor element in second-level polycrystalline silicon
Assignee: Texas Instruments Inc
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Filing: 1979-06-15
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Granted: 1981-09-22
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Expires: 1999-06-15
Abstract
Abstract Integrated circuit resistor elements ideally suited for load devices in static MOS RAM cells are made in second-level polycrystalline silicon by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The second-level polysilicon is insulated from first-level polysilicon by multi-layer insulation; first, a thermal oxide layer provides better edge breakdown characteristics for transistors, then secondly a layer of doped deposited oxide provides improved step coverage, and finally an undoped deposited oxide is used to prevent out diffusion from doped oxide to second level polysilicon which would change the characteristics of the resistors.
Inventors
- 👤 Jih-Chang Lien
- 👤 Te-Long Chiu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:28
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10D88/00; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6306; H10P14/6308; H10W; H10W20/00; H10W20/01; H10W20/40; H10W20/45; H10W20/48
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
110 words
In a semiconductor integrated circuit, (a) a first level of polycrystalline silicon overlying a face of a semiconductor body and patterned to define electrodes of circuit elements and interconnections between electrodes, (b) a second level of polycrystalline silicon overlying said face and at least partially overlying said first level of polycrystalline silicon, said second level being patterned to define parts of circuit elements and interconnections, (c) and a triple layer insulator separating said first and second levels of polycrystalline silicon, the first layer being thermal silicon oxide on the first level, the second layer being doped low-temperature deposited silicon oxide and the third layer being undoped low-temperature deposited silicon oxide.
Claim 2
Dependent Claim
110 words
In a semiconductor integrated circuit, (a) a first level of polycrystalline silicon overlying a face of a semiconductor body and patterned to define electrodes of circuit elements and interconnections between electrodes, (b) a second level of polycrystalline silicon overlying said face and at least partially overlying said first level of polycrystalline silicon, said second level being patterned to define parts of circuit elements and interconnections, (c) and a triple layer insulator separating said first and second levels of polycrystalline silicon, the first layer being thermal silicon oxide on the first level, the second layer being doped low-temperature deposited silicon oxide and the third layer being undoped low-temperature deposited silicon oxide.
Claim 3
Dependent Claim
33 words
In a device according to claim 1, the body being silicon, the circuit elements including MOS transistors, the electrodes including gates of such MOS transistors, said parts of circuit elements including implanted resistors.
Claim 4
Dependent Claim
19 words
In a device according to claim 2, the second layer having areas much more heavily doped than selected areas.
Claim 5
Dependent Claim
13 words
In a device according to claim 3, the selected areas being resistor regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |