US4110776A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit with implanted resistor element in polycrystalline silicon layer
Assignee: Texas Instruments Inc
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Filing: 1976-09-27
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Granted: 1978-08-29
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Expires: 1996-09-27
Abstract
Abstract Resistor elements for MOS integrated circuits are made by an ion implant step compatible with a self-aligned N-channel silicon-gate process. The resistor elements are in a part of a polycrystalline silicon layer which is also used as a gate for an MOS transistor and as an interconnection overlying field oxide. Resistors of this type are ideally suited for load devices in static RAM cells.
Inventors
- 👤 G. R. Mohan Rao
- 👤 John S. Stanczak
- 👤 Jih-Chang Lien
- 👤 Shyam Bhatia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 23:53
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; H10P; H10P32/00; H10P32/30; H10P32/302; H10W; H10W20/00; H10W20/01; H10W20/40; Y; Y10; Y10S; Y10S148/00; Y10S148/136
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
113 words
A resistor element for an N-channel, silicon-gate MOS integrated circuit of the type having field oxide surrounding transistor areas on the face of a semiconductor substrate, the transistor areas having gate oxide much thinner than the field oxide, comprising: a. an elongated strip of polycrystalline silicon extending across the field oxide and contacting at least one of the transistor areas, b. a resistor region in the elongated strip implanted with conductivity determining impurity to provide a selected resistivity less than that of undoped polycrystalline silicon, c. conductive regions in the elongated strip on both ends of the resistor regions, the conductive regions being doped at a level much higher than the resistor region.
Claim 2
Dependent Claim
113 words
A resistor element for an N-channel, silicon-gate MOS integrated circuit of the type having field oxide surrounding transistor areas on the face of a semiconductor substrate, the transistor areas having gate oxide much thinner than the field oxide, comprising: a. an elongated strip of polycrystalline silicon extending across the field oxide and contacting at least one of the transistor areas, b. a resistor region in the elongated strip implanted with conductivity determining impurity to provide a selected resistivity less than that of undoped polycrystalline silicon, c. conductive regions in the elongated strip on both ends of the resistor regions, the conductive regions being doped at a level much higher than the resistor region.
Claim 3
Dependent Claim
38 words
A resistor element according to claim 1 wherein the resistor region is implanted with phosphorus at a dosage of about 5 × 10 13 to 1 × 10 14 atoms per cm 2 at 100 to 150 KeV.
Claim 4
Dependent Claim
20 words
A resistor element according to claim 2 wherein the polycrystalline silicon is no more than about 0.5 micron in thickness.
Claim 5
Dependent Claim
18 words
A resistor element according to claim 3 wherein a silicon oxide coating is provided on the resistor region.
Claim 6
Dependent Claim
131 words
In a static RAM cell of the type formed in a semiconductor integrated circuit having a semiconductor substrate, a pair of driver transistors formed in the substrate at one face thereof, a pair of load devices, first conductive means at said one face connecting each of the driver transistors in series with one of the load devices, second conductive means at said one face cross-coupling an output electrode of each driver transistor to a control electrode of the other driver transistor, the improvement wherein resistor elements providing said load devices comprise lightly-doped ion-implanted polycrystalline semiconductor material overlying an insulating coating on said one face said material being doped to a level which provides a selected resistivity less than that of undoped polycrystalline semiconductor and much greater than that of diffused semiconductor.
Claim 7
Dependent Claim
131 words
In a static RAM cell of the type formed in a semiconductor integrated circuit having a semiconductor substrate, a pair of driver transistors formed in the substrate at one face thereof, a pair of load devices, first conductive means at said one face connecting each of the driver transistors in series with one of the load devices, second conductive means at said one face cross-coupling an output electrode of each driver transistor to a control electrode of the other driver transistor, the improvement wherein resistor elements providing said load devices comprise lightly-doped ion-implanted polycrystalline semiconductor material overlying an insulating coating on said one face said material being doped to a level which provides a selected resistivity less than that of undoped polycrystalline semiconductor and much greater than that of diffused semiconductor.
Claim 8
Dependent Claim
13 words
A device according to claim 5 wherein the resistor elements are phosphorus implanted.
Claim 9
Dependent Claim
25 words
A device according to claim 5 wherein the substrate is silicon and the driver transistors are surrounded on said one face by thermally-grown silicon oxide.
Claim 10
Dependent Claim
25 words
A device according to claim 7 wherein the first conductive means and the second conductive means comprise polycrystalline silicon which is heavily doped with phosphorus.
Claim 11
Dependent Claim
39 words
A device according to claim 8 wherein the first and second conductive means include an elongated continuous strip of silicon which extends from the control electrode of the driver transistor to the control electrode of the other driver transistor.
Claim 12
Independent Claim
15 words
A device according to claims 9 wherein the driver transistors are N-channel silicon-gate MOS transistors.
Claim 13
Dependent Claim
19 words
A device according to claim 10 wherein the resistor elements are no greater than about 0.5 micron in thickness.
Claim 14
Dependent Claim
58 words
A device according to claim 11 wherein the resistor elements have an impurity concentration corresponding to an implant dosage of at least about 5 × 10 13 atoms per cm 2 and not more than about 10 14 atoms per cm 2 at an energy level of at least about 100 KeV and not over about 150 KeV.
Claim 15
Dependent Claim
20 words
A device according to claim 12 wherein a protective coating is provided over the polycrystalline silicon of the resistor elements.
Claim 16
Dependent Claim
18 words
A device according to claim 13 wherein the protective coating is thermal silicon oxide or deposited silicon nitride.
Claim 17
Dependent Claim
22 words
A device according to claim 10 wherein the transistors are formed in a continuous moat along with a pair of data-input transistors.
Claim 18
Dependent Claim
28 words
A device according to claim 15 wherein the continuous moat forms a closed figure which additionally includes two driver transistors and two data-input transistors for an adjacent cell.
Claim 19
Dependent Claim
45 words
A device according to claim 16 wherein said elongated continuous strip of silicon is joined at a central location to another similar elongated continuous strip of polycrystalline silicon which provides resistor elements and conductive means as well as silicon gates for a different adjacent cell.
Claim 20
Dependent Claim
99 words
A resistor element for an integrated circuit comprising: an elongated thin strip of polycrystalline silicon having a resistor portion which is lightly doped and conductor portions which are heavily doped, the resistor portion being ion implanted to a concentration corresponding to a dosage of at least about 5 × 10 13 and not more than about 10 14 phosphorus atoms per cm 2 at an energy level of at least about 100 KeV and not over about 150 KeV, the conductor portions being phosphorus diffused at a concentration many orders of magnitude greater than that of the resistor portions.
Claim 21
Dependent Claim
99 words
A resistor element for an integrated circuit comprising: an elongated thin strip of polycrystalline silicon having a resistor portion which is lightly doped and conductor portions which are heavily doped, the resistor portion being ion implanted to a concentration corresponding to a dosage of at least about 5 × 10 13 and not more than about 10 14 phosphorus atoms per cm 2 at an energy level of at least about 100 KeV and not over about 150 KeV, the conductor portions being phosphorus diffused at a concentration many orders of magnitude greater than that of the resistor portions.
Claim 22
Dependent Claim
21 words
A device according to claim 18 wherein the strip of polycrystalline silicon is no more than about 0.5 micron in thickness.
Claim 23
Dependent Claim
56 words
A device according to claim 18 wherein the resistor portion is ion implanted to a concentration corresponding to a dosage of at least about 5 × 10 13 and not more than about 10 14 phosphorus atoms per cm 2 at an energy level of at least about 100 KeV and not over about 150 KeV.
Claim 24
Dependent Claim
27 words
A device according to claim 20 wherein the conductor portions are phosphorus diffused at a concentration many orders of magnitude greater than that of the resistor portions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |