US4246692A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MOS Integrated circuits with implanted resistor elements
Assignee: Texas Instruments Inc
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Filing: 1976-05-28
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Granted: 1981-01-27
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Expires: 1996-05-28
Abstract
Abstract Resistor elements for MOS integrated circuits are made by an ion implant step compatable with a self-aligned N-channel silicon-gate process. The resistor elements are beneath the field oxide in the finished device, although the implant step is prior to formation of the thick oxide. Resistors of this type are ideally suited for load devices in static RAM cells.
Inventors
- 👤 G. R. Mohan Rao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:42
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H; H10; H10B; H10B10/00; H10B10/15; H10D; H10D1/00; H10D1/40; H10D1/43; H10D84/00; H10D84/80; H10D84/811; H10D84/817
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
220 words
A method of making resistor elements in N-channel, silicon-gate MOS integrated circuit devices, comprising the steps of: growing a thin silicon oxide coating on a surface of a monocrystalline silicon slice containing a first conductivity type determining impurity; covering the thin silicon oxide coating with a thin layer of silicon nitride; removing the silicon nitride coating in a pattern to expose selected resistor areas; implanting a second conductivity-type determining impurity opposite the first type into a shallow surface-adjacent region of the silicon in said resistor areas by exposing the slice to an ion beam, such implanting being done through said thin silicon oxide coating; subjecting the slice to an elevated temperature in an inert atmosphere to raise the concentration of the first impurity below said surface-adjacent region; oxidizing the slice at an elevated temperature for a time exceeding that used in the prior step to create a thick silicon oxide coating in said exposed areas and covering the resistor areas; forming an electrical connection to each of a plurality of spaced portions of the implanted region in said resistor area; removing the remaining silicon nitride from the surface of the slice; and forming MOS transistors on said slice by diffusing or implanting into the slice said second conductivity-type determining impurity creating regions in the slice continguous to said resistor areas.
Claim 2
Independent Claim
220 words
A method of making resistor elements in N-channel, silicon-gate MOS integrated circuit devices, comprising the steps of: growing a thin silicon oxide coating on a surface of a monocrystalline silicon slice containing a first conductivity type determining impurity; covering the thin silicon oxide coating with a thin layer of silicon nitride; removing the silicon nitride coating in a pattern to expose selected resistor areas; implanting a second conductivity-type determining impurity opposite the first type into a shallow surface-adjacent region of the silicon in said resistor areas by exposing the slice to an ion beam, such implanting being done through said thin silicon oxide coating; subjecting the slice to an elevated temperature in an inert atmosphere to raise the concentration of the first impurity below said surface-adjacent region; oxidizing the slice at an elevated temperature for a time exceeding that used in the prior step to create a thick silicon oxide coating in said exposed areas and covering the resistor areas; forming an electrical connection to each of a plurality of spaced portions of the implanted region in said resistor area; removing the remaining silicon nitride from the surface of the slice; and forming MOS transistors on said slice by diffusing or implanting into the slice said second conductivity-type determining impurity creating regions in the slice continguous to said resistor areas.
Claim 3
Dependent Claim
24 words
A method according to claim 1 wherein the silicon slice is predominantly of P-type of low impurity concentration, and the second impurity is phosphorus.
Claim 4
Dependent Claim
34 words
A method according to claim 2 wherein the step of subjecting the slice to an ion implant is at a dosage equivalent to about 2 to 6×10 11 /cm 2 at about 150 KeV.
Claim 5
Dependent Claim
19 words
A method according to claim 3 wherein the dosage is no more than about 3×10 11 /cm 2 .
Claim 6
Dependent Claim
37 words
A method according to claim 2 wherein the step of implanting produces a dosage of no more than the equivalent of about 4×10 11 atoms of phosphorus per square centimeter at an energy of about 150 KeV.
Claim 7
Dependent Claim
33 words
A method according to claim 1 wherein the step of oxidizing the slice consumes part of said shallow surface-adjacent region produced by the step of implanting and drives impurities deeper into the slice.
Claim 8
Independent Claim
78 words
A method making resistor elements in a silicon slice in manufacture of MOS integrated circuits of the type having MOS transistors, comprising: implanting conductivity-type determining impurity material in selected resistor areas at the surface of the silicon slice; and thereafter oxidizing selected regions of said surface by heating the slice in an oxidizing atmosphere, producing thick field oxide which covers said selected resistor areas, and forming said MOS transistors with gate oxide much thinner than the field oxide.
Claim 9
Independent Claim
78 words
A method making resistor elements in a silicon slice in manufacture of MOS integrated circuits of the type having MOS transistors, comprising: implanting conductivity-type determining impurity material in selected resistor areas at the surface of the silicon slice; and thereafter oxidizing selected regions of said surface by heating the slice in an oxidizing atmosphere, producing thick field oxide which covers said selected resistor areas, and forming said MOS transistors with gate oxide much thinner than the field oxide.
Claim 10
Dependent Claim
30 words
A method according to claim 7 wherein contact areas are formed in said surface of the slice by diffusing said conductivity-type determining impurity into regions contiguous to the resistor areas.
Claim 11
Dependent Claim
30 words
A method according to claim 8 wherein the implanting is of equivalent to a dosage of about 2 to about 4×10 11 phosphorus atoms per cm 2 at 150 KeV.
Claim 12
Independent Claim
113 words
A method of making a circuit element in a semiconductor integrated circuit, comprising the steps of: implanting conductivity-type determining impurity material in a selected area in a face of a semiconductor body to produce an implanted region of opposite conductivity-type from the bulk of the body; covering the face of the body with a thick oxide coating by heating in an oxidizing atmosphere, consuming the bulk of said region and driving said impurity material further into said face of the body, while masking contact areas on opposite ends of the selected area to prevent oxidation thereof; and introducing conductivity-type determining impurity into the contact areas to provide electrical connection to the circuit element.
Claim 13
Independent Claim
113 words
A method of making a circuit element in a semiconductor integrated circuit, comprising the steps of: implanting conductivity-type determining impurity material in a selected area in a face of a semiconductor body to produce an implanted region of opposite conductivity-type from the bulk of the body; covering the face of the body with a thick oxide coating by heating in an oxidizing atmosphere, consuming the bulk of said region and driving said impurity material further into said face of the body, while masking contact areas on opposite ends of the selected area to prevent oxidation thereof; and introducing conductivity-type determining impurity into the contact areas to provide electrical connection to the circuit element.
Claim 14
Dependent Claim
20 words
A method according to claim 10 wherein the semiconductor body is predominately P-type silicon and the impurity material is phosphorus.
Claim 15
Dependent Claim
31 words
A method according to claim 11 wherein the step of introducing is diffusion which uses another mask of silicon oxide much thinner than said thick oxide to define other circuit components.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-01-27 | 1984-07-28 | 1985-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-01-27 | 1988-07-28 | 1989-01-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-01-27 | 1992-07-28 | 1993-01-27 | $7700.00 | Window Closed / Lapsed |