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US3889358A Expired / Lapsed US ⏱️ 0.0 years remaining

Process for the production of high value ohmic load resistors and mos transistors having a low starting voltage

Assignee: Siemens AG
•
Filing: 1973-09-14
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Granted: 1975-06-17
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Expires: 1993-09-14
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Abstract

Abstract In a process for the production of circuits having at least one field effect transistor including a source, a drain, and a gate electrode, and having a resistor on a common substrate in which, starting with a substrate body having at least one field effect transistor, the process includes the formation of an enhancement type field effect transistor by ion implantation in the channel to decrease the starting voltage and the formation of the resistor by ion implantation adjacent the field effect transistor, wherein the resistor has a value which is high in comparison with the forward resistance of the conductive field effect transistor and low in comparison with the reverse resistance of the field effect transistor.

Inventors

  • 👤 Hartwig Bierhenke

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 18:51
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/811; H10D84/817; H10D99/00

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 157 words
A process for the production of circuits having at least one field effect transistor with a source, a drain, and a gate, and having a resistor, on a common substrate, which process begins with a substrate body having at least one field effect transistor with source, drain and connection zones formed by diffusion, comprising the steps of: implanting ions adjacent the field effect transistor to produce a resistor, and simultaneously implanting ions in the channel zone of the field effect transistor to decrease the starting voltage of the field effect transistor and form an enhancement type field effect transistor, the simultaneous ion implantation comprising an ion implantation of a predetermined ion type with a predetermined ion energy and within a predetermined ion dosage range, the resistor possessing a value which is high in comparison to the forward resistance of the conductive field effect transistor and low in comparison to the reverse resistance of the field effect transistor.
Claim 2
Dependent Claim 157 words
A process for the production of circuits having at least one field effect transistor with a source, a drain, and a gate, and having a resistor, on a common substrate, which process begins with a substrate body having at least one field effect transistor with source, drain and connection zones formed by diffusion, comprising the steps of: implanting ions adjacent the field effect transistor to produce a resistor, and simultaneously implanting ions in the channel zone of the field effect transistor to decrease the starting voltage of the field effect transistor and form an enhancement type field effect transistor, the simultaneous ion implantation comprising an ion implantation of a predetermined ion type with a predetermined ion energy and within a predetermined ion dosage range, the resistor possessing a value which is high in comparison to the forward resistance of the conductive field effect transistor and low in comparison to the reverse resistance of the field effect transistor.
Claim 3
Dependent Claim 32 words
The process set forth in claim 1, comprising the steps of providing n-conducting 10 Omega cm silicon as the substrate; and diffusing p-conducting zones for the respective source, drain and connection zones.
Claim 4
Dependent Claim 22 words
The process as set forth in claim 1, wherein the steps of implanting ions are further defined as implanting positive boron ions.
Claim 5
Dependent Claim 43 words
The process as set forth in claim 1, wherein the step of implanting ions is further defined as implanting ions with an energy of approximately 38 keV and of a dosage from between 7 X 1011 to 1.2 X 1012 ions per cm2.
Claim 6
Dependent Claim 32 words
The process as set forth in claim 1, comprising the step of providing p-conducting silicon as the substrate; and diffusing n-conducting zones into the substrate for the source, drain and connection zones.
Claim 7
Dependent Claim 22 words
The process as set forth in claim 5 wherein the steps of ion implantation are further defined as implanting negative phosphorus ions.
Claim 8
Dependent Claim 302 words
A process for the production of circuits having at least one field effect transistor with a source, a drain, and a gate, and having a resistor, on a common substrate, which process begins with a substrate body having at least one field effect transistor with source, drain and connection zones formed by diffusion, comprising the steps of: implanting ions adjacent the field effect transistor to produce a resistor, and implanting ions in the channel zone of the field effect transistor to decrease the sTarting voltage of the field effect transistor and form an enhancement type field effect transistor, the resistor possessing a value which is high in comparison to the forward resistance of the conductive field effect transistor and low in comparison to the reverse resistance of the field effect transistor, the process being more specifically defined by the steps of applying a thick oxide layer to the substrate, removing portions of the thick oxide layer in those regions under which the source, drain and connection zones are to be produced, diffusing the substrate to form the source, drain and connection zones, doping the source, drain and connection zones by diffusion, removing the thick oxide layer above the regions into which ions are to be implanted and during this step simultaneously removing the oxide layers which have formed during diffusion above the source, drain and connection zones, applying a thin oxide layer to those regions which are now exposed, implanting ions through the thin oxide layer to form a resistor which extends from the connection zone to one of the other diffused zones, removing the thin oxide layer at the points at which the diffused zones are to be contacted, the connection zones serving as a contact for the resistor, and forming conductor paths and electrodes to those points by vapor deposition.
Claim 9
Dependent Claim 302 words
A process for the production of circuits having at least one field effect transistor with a source, a drain, and a gate, and having a resistor, on a common substrate, which process begins with a substrate body having at least one field effect transistor with source, drain and connection zones formed by diffusion, comprising the steps of: implanting ions adjacent the field effect transistor to produce a resistor, and implanting ions in the channel zone of the field effect transistor to decrease the sTarting voltage of the field effect transistor and form an enhancement type field effect transistor, the resistor possessing a value which is high in comparison to the forward resistance of the conductive field effect transistor and low in comparison to the reverse resistance of the field effect transistor, the process being more specifically defined by the steps of applying a thick oxide layer to the substrate, removing portions of the thick oxide layer in those regions under which the source, drain and connection zones are to be produced, diffusing the substrate to form the source, drain and connection zones, doping the source, drain and connection zones by diffusion, removing the thick oxide layer above the regions into which ions are to be implanted and during this step simultaneously removing the oxide layers which have formed during diffusion above the source, drain and connection zones, applying a thin oxide layer to those regions which are now exposed, implanting ions through the thin oxide layer to form a resistor which extends from the connection zone to one of the other diffused zones, removing the thin oxide layer at the points at which the diffused zones are to be contacted, the connection zones serving as a contact for the resistor, and forming conductor paths and electrodes to those points by vapor deposition.

References Cited (Backward Citations)

US3605256A Cited
US3655457A Cited
US3679492A Cited
US3789504A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-06-16 1978-12-16 1979-06-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-06-16 1982-12-16 1983-06-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-06-16 1986-12-16 1987-06-17 $7700.00 Window Closed / Lapsed

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