Method of manufacturing an n-channel mos field-effect transistor

Claim 2

A process for forming an n-channel enhancement field-effect semiconductor device comprising the steps of: a. forming two spaced apart regions of n-type conductivity in a substrate having p-type conductivity; b. implanting a layer of material of p-type conductivity in said substrate between said n-type regions, said layer being located at a predetermined depth below the surface of said substrate; c. forming a layer of insulating material on the surface of said substrate, said insulating layer overlaying said layer of ptype material and at least partially overlaying said n-type regions; d. diffusing said material of p-type conductivity in said implanted layer towaRd the surface of said substrate at the same time as forming said layer of insulating material; and e. forming three layers of a conductive material, the first of said layers being formed on said insulating layer, the second and third layers of conductive material being formed individually in the n-type regions.

Claim 3

The process of claim 1 wherein the resistivity of said substrate is at least 100 ohm-cm.

Claim 4

The process of claim 1 wherein said implanted material having p-type conductivity is boron.

Claim 5

The process of claim 1 which includes an initial step of diffusing a sheet of p-type conductivity material in the surface of silicon to form a substrate having p-type conductivity.

Claim 6

The process of claim 4 wherein said sheet of p-type conductivity has a resistivity of about 1300 ohms/square centimeters.

Claim 7

The process of claim 1 wherein said layers of conductive material are aluminum.

Claim 8

The process of claim 1 wherein said layer of insulating material is silicon dioxide.

Claim 9

In a method of manufacturing an n-channel enhancement field-effect transistor having a drain, source, and channel region at the surface of a semiconductive substrate, said channel region located between said drain and source region, the improvement comprises forming the channel region by: ion implanting a layer of p-type conductive material a predetermined depth beneath the surface of said substrate in the channel region; heating said implanted substrate in an oxygen atmosphere to form an insulative oxide layer above said implanted layer and extending at least partially over said drain and source regions; and diffusing said implanted material toward the surface of said substrate at the same time as heating the substrate.

Claim 10

In a method of manufacturing an n-channel enhancement field-effect transistor having a drain, source, and channel region at the surface of a semiconductive substrate, said channel region located between said drain and source region, the improvement comprises forming the channel region by: ion implanting a layer of p-type conductive material a predetermined depth beneath the surface of said substrate in the channel region; heating said implanted substrate in an oxygen atmosphere to form an insulative oxide layer above said implanted layer and extending at least partially over said drain and source regions; and diffusing said implanted material toward the surface of said substrate at the same time as heating the substrate.

Claim 11

A process for making an n-channel enhancement field-effect semiconductor device comprising the steps of: a. forming a thin sheet of p-type conductivity material in the surface of a silicon substrate; b. diffusing material of n-type conductivity into two regions spaced apart in the p-type surface of the substrate; c. ion implanting a layer of p-type conductive material between said n-type regions at a predetermined depth beneath the surface of said substrate; d. heating said implanted substrate to a first temperature in a wet oxygen atmosphere to rapidly grow a silicon dioxide layer of insulating material and to control the diffusion of the implanted material, said silicon dioxide layer being located on the surface of said substrate overlaying said implanted layer and at least partially overlaying said n-type regions; and e. depositing three layers of conductive material, the first of said layers overlaying said insulating layer, and the second and third layers of conductive material being formed individually in contact with the n-type regions.

Claim 12

A process for making an n-channel enhancement field-effect semiconductor device comprising the steps of: a. forming a thin sheet of p-type conductivity material in the surface of a silicon substrate; b. diffusing material of n-type conductivity into two regions spaced apart in the p-type surface of the substrate; c. ion implanting a layer of p-type conductive material between said n-type regions at a predetermined depth beneath the surface of said substrate; d. heating said implanted substrate to a first temperature in a wet oxygen atmosphere to rapidly grow a silicon dioxide layer of insulating material and to control the diffusion of the implanted material, said silicon dioxide layer being located on the surface of said substrate overlaying said implanted layer and at least partially overlaying said n-type regions; and e. depositing three layers of conductive material, the first of said layers overlaying said insulating layer, and the second and third layers of conductive material being formed individually in contact with the n-type regions.

Claim 13

The process of claim 9 which includes after step (d) the additional step of heating said substrate to a second temperature in a dry oxygen atmosphere to diffuse said implanted material toward the surface of said substrate and to control the growth of the silicon dioxide layer.

Claim 14

The process of claim 10 wherein the first temperature is lower than the second temperature.

Claim 15

The process of claim 10 wherein the first temperature is 950*C and the second temperature is 1050*C.