US3605256A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a transistor and transistor manufactured by this method
Assignee: Individual
•
Filing: 1968-10-02
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Granted: 1971-09-20
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Expires: 1988-10-02
Abstract
Abstract A METHOD OF MANUFACTURING A DOUBLE-DIFFUSED TRANSISTOR USING AN INTEGRAL MASKING LAYER BY THE SO-CALLED PLANAR PROCESS IN WHICH, AFTER THE EMITTER REGION IS FORMED BY DIFFUSION THROUGH AN EMITTER WINDOW IN THE MASKING LAYER, THE EARLIER PROVIDED BASE WINDOW IS ENTIRELY REOPENED EXPOSING THE EMITTER BASE JUNCTION AT THE SURFACE, FOLLOWING WHICH A SECOND MASKING LAYER IS PROVIDED ON THE EXPOSED SEMICONDUCTOR SURFACE AND WINDOWS ESTABLISHED THEREIN FOR PROVIDING CONTACTS TO THE EMITTER AND BASE REGIONS.
Inventors
- 👤 Albert Schmitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 00:05
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; H10D84/615; H10W; H10W20/00; H10W20/40; H10W74/00; H10W74/40; H10W74/43; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/085; Y10S148/106
Claims Analysis
Total Claims: 0
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References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-09-19 | 1975-03-21 | 1975-09-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-09-19 | 1979-03-21 | 1979-09-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-09-19 | 1983-03-21 | 1983-09-20 | $7700.00 | Window Closed / Lapsed |