Method of making non-volatile semiconductor memory device with the floating gate having upper and lower impurity concentrations

Claim 1

A method for manufacturing a non-volatile semiconductor memory device including the steps of forming a plurality of diffused layers in a semiconductor substrate, each adjacent two of said diffused layers forming a channel region, forming a plurality of field insulating films extending parallel to one another in a row direction to divide each of said channel regions into a plurality of channels, forming a first polycrystalline silicon film insulated from said semiconductor substrate and including a lower layer having a first impurity concentration and an upper layer having a second impurity concentration which is higher than said first impurity concentration, patterning said first polycrystalline silicon film into a plurality of first strip films extending parallel to one another in said column direction, forming a second polycrystalline silicon film and patterning the same to form a second strip film overlying said first strip films and extending parallel to one another in said row direction, patterning each of said first strip films into a plurality of floating gates arranged in a matrix, each of said floating gates being disposed in an operative relationship with a corresponding one of said channels, wherein the upper and lower layer have an even thickness.

Claim 2

A method for manufacturing a non-volatile semiconductor memory device including the steps of forming a plurality of diffused layers in a semiconductor substrate, each adjacent two of said diffused layers forming a channel region, forming a plurality of field insulating films extending parallel to one another in a row direction to divide each of said channel regions into a plurality of channels, forming a first polycrystalline silicon film insulated from said semiconductor substrate and including a lower layer having a first impurity concentration and an upper layer having a second impurity concentration which is higher than said first impurity concentration, patterning said first polycrystalline silicon film into a plurality of first strip films extending parallel to one another in said column direction, forming a second polycrystalline silicon film and patterning the same to form a second strip film overlying said first strip films and extending parallel to one another in said row direction, patterning each of said first strip films into a plurality of floating gates arranged in a matrix, each of said floating gates being disposed in an operative relationship with a corresponding one of said channels, wherein the upper and lower layer have an even thickness.

Claim 4

A method for manufacturing a nonvolatile semiconductor memory device including the steps of forming a plurality of diffused layers in a semiconductor substrate, each adjacent two of said diffused layers forming a channel region, forming a plurality of field insulating films extending parallel to one another in a row direction to divide each of said channel regions into a plurality of channels, forming a first polycrystalline silicon film insulated from said semiconductor substrate and including a lower layer having a first impurity concentration and an upper layer having a second impurity concentration which is higher than said first impurity concentration, patterning said first polycrystalline silicon film into a plurality of first strip films extending parallel to one another in said column direction, forming a second polycrystalline silicon film and patterning the same to form a second strip film overlying said first strip films and extending parallel to one another in said row direction, patterning each of said first strip films into a plurality of floating gates arranged in a matrix, each of said floating gates being disposed in an operative relationship with a corresponding one of said channels, wherein a thickness of said lower layer is substantially the same as a thickness of said field insulating films.

Claim 5

A method for manufacturing a nonvolatile semiconductor memory device including the steps of forming a plurality of diffused layers in a semiconductor substrate, each adjacent two of said diffused layers forming a channel region, forming a plurality of field insulating films extending parallel to one another in a row direction to divide each of said channel regions into a plurality of channels, forming a first polycrystalline silicon film insulated from said semiconductor substrate and including a lower layer having a first impurity concentration and an upper layer having a second impurity concentration which is higher than said first impurity concentration, patterning said first polycrystalline silicon film into a plurality of first strip films extending parallel to one another in said column direction, forming a second polycrystalline silicon film and patterning the same to form a second strip film overlying said first strip films and extending parallel to one another in said row direction, patterning each of said first strip films into a plurality of floating gates arranged in a matrix, each of said floating gates being disposed in an operative relationship with a corresponding one of said channels, wherein a thickness of said lower layer is substantially the same as a thickness of said field insulating films.