US5365098A
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US
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Non-volatile semiconductor memory having improved erasure characteristics
Assignee: Toshiba Corp
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Filing: 1992-10-20
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Granted: 1994-11-15
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Expires: 2012-10-20
Abstract
Abstract A floating gate is formed via a first gate insulating film over the channel region between source and drain regions which are formed in a semiconductor substrate. A control gate is formed via a second gate insulating film over the floating gate. A low impurity concentration semiconductor region is formed on the side of the control gate which faces the floating gate. When erasing, a depletion layer is produced in this low impurity concentration region and further saturates the erase characteristic for the erasure time by decreasing the capacitance between the control gate and the floating gate.
Inventors
- 👤 Junichi Miyamoto
- 👤 Kuniyoshi Yoshikawa
- 👤 Kiyomi Naruke
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 21:08
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/80; H10D84/82; H10D84/83; H10D84/834
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
159 words
A non-volatile semiconductor memory comprising a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode over the channel region; and a control gate electrode including polycrystalline silicon of the first conductivity type, means for reducing a capacitance between the floating gate electrode and the control gate electrode when a voltage is applied between the source region and the control gate electrode, the reducing means comprising a depletion layer at a side of the control gate electrode facing the floating gate electrode, wherein the control gate electrode comprises a floating gate electrode side and an upper side on the floating gate electrode side, and an impurity concentration of the floating gate electrode side is lower than an impurity concentration of the upper side.
Claim 2
Dependent Claim
159 words
A non-volatile semiconductor memory comprising a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode over the channel region; and a control gate electrode including polycrystalline silicon of the first conductivity type, means for reducing a capacitance between the floating gate electrode and the control gate electrode when a voltage is applied between the source region and the control gate electrode, the reducing means comprising a depletion layer at a side of the control gate electrode facing the floating gate electrode, wherein the control gate electrode comprises a floating gate electrode side and an upper side on the floating gate electrode side, and an impurity concentration of the floating gate electrode side is lower than an impurity concentration of the upper side.
Claim 3
Dependent Claim
26 words
The non-volatile semiconductor memory of claim 1, wherein the impurity concentration of the floating gate electrode side is not greater than 1×10 20 cm -3 .
Claim 4
Dependent Claim
26 words
The non-volatile semiconductor memory of claim 2, wherein The impurity concentration of the floating gate electrode side is not greater than 1×10 19 cm -3 .
Claim 5
Dependent Claim
25 words
The non-volatile semiconductor memory of claim 1, wherein the impurity concentration of the control gate electrode is not greater than 1×10 20 cm -3 .
Claim 6
Dependent Claim
25 words
The non-volatile semiconductor memory of claim 1, wherein an impurity concentration of the control gate electrode is not greater than 1×10 19 cm -3 .
Claim 7
Dependent Claim
19 words
The non-volatile semiconductor memory of claim 1, further comprising means for reducing a resistance of the control gate electrode.
Claim 8
Dependent Claim
23 words
The non-volatile semiconductor memory of claim 6, wherein the resistance reducing means comprises a metal layer in contact with the control gate electrode.
Claim 9
Dependent Claim
31 words
The non-volatile semiconductor memory of claim 7, the control gate electrode further comprising means for preventing the formation of a Shottky barrier between the capacitance reducing means and the metal layer.
Claim 10
Dependent Claim
164 words
A non-volatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode over the channel region, the floating gate electrode including polycrystalline silicon of the second conductivity type, means for reducing a capacitance between the floating gate electrode and the control gate electrode when a voltage is applied between the source region and the control gate electrode, the reducing means comprises a depletion layer at a side of the floating gate electrode facing the control gate electrode; and a control gate electrode electrically insulated from the floating gate electrode, wherein the floating gate electrode comprises a channel side and an upper side on the channel side, and an impurity concentration of the upper side is lower than an impurity concentration of the channel side.
Claim 11
Dependent Claim
164 words
A non-volatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode over the channel region, the floating gate electrode including polycrystalline silicon of the second conductivity type, means for reducing a capacitance between the floating gate electrode and the control gate electrode when a voltage is applied between the source region and the control gate electrode, the reducing means comprises a depletion layer at a side of the floating gate electrode facing the control gate electrode; and a control gate electrode electrically insulated from the floating gate electrode, wherein the floating gate electrode comprises a channel side and an upper side on the channel side, and an impurity concentration of the upper side is lower than an impurity concentration of the channel side.
Claim 12
Dependent Claim
23 words
The non-volatile semiconductor memory of claim 9, wherein the impurity concentration of the upper side is not greater 1×10 20 cm -3 .
Claim 13
Dependent Claim
24 words
The non-volatile semiconductor memory of claim 10, wherein the impurity concentration of the upper side is not greater than 1×10 19 cm -3 .
Claim 14
Dependent Claim
25 words
The non-volatile semiconductor memory of claim 9, wherein the impurity concentration of the floating gate electrode is not greater than 1×10 20 cm -3 .
Claim 15
Dependent Claim
25 words
The non-volatile semiconductor memory of claim 9, wherein an impurity concentration of the floating gate electrode is not greater than 1×10 19 cm -3 .
Claim 16
Dependent Claim
108 words
A non-volatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode over the channel region; and a control gate electrode of the first conductivity type semiconductor including a first portion opposing the floating gate electrode and a second portion separated from the floating gate electrode by the first portion, wherein an impurity concentration of the first portion is lower than an impurity concentration of the second portion.
Claim 17
Dependent Claim
108 words
A non-volatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode over the channel region; and a control gate electrode of the first conductivity type semiconductor including a first portion opposing the floating gate electrode and a second portion separated from the floating gate electrode by the first portion, wherein an impurity concentration of the first portion is lower than an impurity concentration of the second portion.
Claim 18
Dependent Claim
110 words
A non-volatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode of the second conductivity type semiconductor over the channel region including a first portion opposing the channel region and a second portion separated from the channel region by the first portion, wherein an impurity concentration of the second portion is lower than an impurity concentration of the first portion; and a control gate electrode opposing the second portion.
Claim 19
Dependent Claim
110 words
A non-volatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode of the second conductivity type semiconductor over the channel region including a first portion opposing the channel region and a second portion separated from the channel region by the first portion, wherein an impurity concentration of the second portion is lower than an impurity concentration of the first portion; and a control gate electrode opposing the second portion.
Claim 20
Dependent Claim
97 words
A non-volatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode over the channel region; and a control gate electrode including a floating gate electrode side and an upper side on the floating gate electrode side, and an impurity concentration of the floating gate electrode side is lower than an impurity concentration of the upper side.
Claim 21
Dependent Claim
97 words
A non-volatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode over the channel region; and a control gate electrode including a floating gate electrode side and an upper side on the floating gate electrode side, and an impurity concentration of the floating gate electrode side is lower than an impurity concentration of the upper side.
Claim 22
Dependent Claim
98 words
A non-volatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode over the channel region, including a channel side and an upper side on the channel side, and an impurity concentration of the upper side is lower than an impurity concentration of the channel side; and a control gate electrode electrically insulated from the floating gate electrode.
Claim 23
Dependent Claim
98 words
A non-volatile semiconductor memory comprising: a semiconductor substrate of a first conductivity type having a surface; a source region of a second conductivity type on the surface; a drain region of the second conductivity type on the surface; a channel region between the source and the drain regions; a floating gate electrode over the channel region, including a channel side and an upper side on the channel side, and an impurity concentration of the upper side is lower than an impurity concentration of the channel side; and a control gate electrode electrically insulated from the floating gate electrode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-14 | 1998-05-16 | 1998-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-14 | 2002-05-16 | 2002-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-14 | 2006-05-16 | 2006-11-15 | $7700.00 | Window Closed / Lapsed |