US4947221A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell for a dense EPROM
Assignee: Intersil Corp
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Filing: 1986-12-10
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Granted: 1990-08-07
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Expires: 2006-12-10
Abstract
Abstract A memory cell has a first capacitance between a floating gate and a channel region and a second capacitance between a control gate and the floating gate. The second capacitance is less than said first capacitance, preferably much less, and there is self-alignment in two directions, resulting in a compact cell. The floating gate can have a textured surface facing the control gate. The control gate can also shift the cell operation from the enhancement mode into the depletion mode.
Inventors
- 👤 Roger G. Stewart
- 👤 Alfred C. Ipri
- 👤 Louis S. Napoli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:19
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10B; H10B69/00
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
131 words
A transistor memory cell comprising: a substrate having spaced source and drain regions and a channel region therebetween; a first insulating layer disposed on said channel region; a floating gate disposed on said first insulating layer and coterminous with said channel region in the width axis of the transistor to form a first capacitor having a first capacitance with said substrate; a second insulating layer disposed on said floating gate; and a control gate disposed on said second insulating layer caterminous with said floating gate in the length axis of the transistor to form a second capacitor having a second capacitance with said floating gate, said second capacitance being less than said first capacitance, and wherein said first capacitor has a greater effective area and smaller spacing than said second capacitor.
Claim 2
Dependent Claim
131 words
A transistor memory cell comprising: a substrate having spaced source and drain regions and a channel region therebetween; a first insulating layer disposed on said channel region; a floating gate disposed on said first insulating layer and coterminous with said channel region in the width axis of the transistor to form a first capacitor having a first capacitance with said substrate; a second insulating layer disposed on said floating gate; and a control gate disposed on said second insulating layer caterminous with said floating gate in the length axis of the transistor to form a second capacitor having a second capacitance with said floating gate, said second capacitance being less than said first capacitance, and wherein said first capacitor has a greater effective area and smaller spacing than said second capacitor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-06 | 1994-02-05 | 1994-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-06 | 1998-02-05 | 1998-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-06 | 2002-02-05 | 2002-08-07 | $7700.00 | Window Closed / Lapsed |