Dual word line, electrically alterable, nonvolatile floating gate memory device

Claim 1

A non-volatile electrically erasable, programmable floating gate memory device having a body of semiconductor material of a first conductivity type with extended, parallel source and drain regions of a second conductivity type embedded in the body of semiconductor material at a surface thereof and spaced one from the other to define a channel region, a conductive floating gate member oriented parallel to said surface and insulated from the substrate and having a portion thereof disposed over the channel region, a conductive program line having a portion thereof disposed over and insulated from the floating gate member and a conductive word line disposed over and insulated from the conductive program line, comprising: a portion of the floating gate being oriented in a direction parallel to the extended source and drain regions and aligned with the channel region; the program line being disposed under and parallel to the word line over the channel region with both lines perpendicularly disposed with respect to the orientation of the floating gate; the ends of the floating gate being aligned with the width of the word line; and the capacitance values of the floating gate, the word and program lines and the substrate having the relationship: C.sub.2 <C.sub.3 >C.sub.1 where: C 1 =the floating gate-to-substrate capacitance, C 2 =the program line-to-floating gate capacitance; and C 3 =the word line-to-floating gate capacitance.