Virtual ground memory cell array

Claim 1

An array of nonvolatile memory cells, comprising: a semiconductor layer of a first conductivity type; a number of memory cells, each cell having at least one transistor, with a source region, a drain region, a floating gate, and a control gate; a number of row lines for connecting the control gates of each row of cells of said array; a number of column lines for connecting the drain regions of columns of cells of said array, and the source regions of the next adjacent column of cells of said array; such that row-adjacent cell-pairs share a column line; wherein each column line has a first junction with the source/drain of one cell of its associated cell-pair that is abrupt and has a second junction with the source/drain of the other cell of its associated cell-pair that is graded; and wherein said source regions and drain regions are buried under thermal insulator regions.