Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth

Claim 2

A process for fabricating an array of floating gate memory devices on a substrate comprising the steps of: forming elongated, spaced-apart, parallel strips of silicon nitride over first regions of said substrate, said strips of silicon nitride defining elongated, parallel, spaced-apart second regions of said substrate between said strips; doping said second regions of said substrate between said strips such that alternate ones of said second regions are doped with an n-type dopant to a first level of doping and the others of said second regions are doped with an n-type dopant to a second level of doping, said first level of doping being different from said second level of doping; growing first oxide regions at said second regions in a wet oxidation process wherein H 2 O from said wet oxidation process reacts with said strips of silicon nitride to form a compound, said compound further reacting with said substrate to form a thin silicon nitride layer disposed on the surface of said substrate in tunneling regions, said thin silicon nitride layer inhibiting lateral growth of said first oxide regions during subsequent oxidation steps; removing said silicon nitride strips; growing second oxide regions at said first regions of said substrate, said second oxide regions being the first thermally grown silicon dioxide layer in said first regions following the removal of said silicon nitride strips; forming a plurality of first gate members from a first layer of polysilicon, said first gate members being disposed over said first regions and being insulated from said first regions by said second oxide regions; forming elongated second gate members from a second layer of polysilicon, said second gate members being formed over said first gate members and being insulated from said first gate members, said second gate members being generally perpendicular to said first and second regions.

Claim 3

The process as in claim 1 wherein said doping step comprises steps of: implanting an arsenic dopant into all of said second regions; implanting a phosphorous dopant into alternate ones of said second regions.

Claim 4

The process as in claim 1 wherein said second oxide regions are approximately 110 angstroms thick.

Claim 5

The process as in claim 2 wherein said second oxide regions are approximately 110 angstroms thick.

Claim 6

A process for fabricating an array of floating gate memory devices on a substrate comprising the steps of: forming elongated, spaced-apart, parallel strips of silicon nitride over first regions of said substrate, said strips of silicon nitride defining elongated, parallel, spaced-apart second regions of said substrate between said strips; doping said second regions of said substrate between said strips such that alternate ones of said second regions are doped with an n-type dopant to a first depth and the others of said second regions are doped with an n-type dopant to a second depth, said first depth being greater than said second depth; growing first oxide regions at said second regions of said substrate in a wet oxidation process wherein H 2 O from said wet oxidation process reacts with said strips of silicon nitride to form a compound, said compound further reacting with said substrate to form a thin silicon nitride layer disposed on the surface of said substrate in tunneling regions, said thin silicon nitride layer inhibiting lateral growth of said first oxide regions during subsequent oxidation steps; removing said silicon nitride strips: growing second oxide regions at said first regions of said substrate, said second oxide regions being the first thermally grown silicon dioxide layer in said first regions following the removal of said silicon nitride strips; forming a plurality of first gate members from a first layer of polysilicon, said first gate members being disposed over said first regions of said substrate and being insulated from said first regions of said substrate by said second oxide regions; forming elongated second gate members from a second layer of polysilicon, said second gate members being formed over said first gate members and being insulated from said first gate members, said second gate members being generally perpendicular to said first and said second regions of said substrate.

Claim 7

A process for fabricating an array of floating gate memory devices on a substrate comprising the steps of: forming elongated, spaced-apart, parallel strips of silicon nitride over first regions of said substrate, said strips of silicon nitride defining elongated, parallel, spaced-apart second regions of said substrate between said strips; doping said second regions of said substrate between said strips such that alternate ones of said second regions are doped with an n-type dopant to a first depth and the others of said second regions are doped with an n-type dopant to a second depth, said first depth being greater than said second depth; growing first oxide regions at said second regions of said substrate in a wet oxidation process wherein H 2 O from said wet oxidation process reacts with said strips of silicon nitride to form a compound, said compound further reacting with said substrate to form a thin silicon nitride layer disposed on the surface of said substrate in tunneling regions, said thin silicon nitride layer inhibiting lateral growth of said first oxide regions during subsequent oxidation steps; removing said silicon nitride strips: growing second oxide regions at said first regions of said substrate, said second oxide regions being the first thermally grown silicon dioxide layer in said first regions following the removal of said silicon nitride strips; forming a plurality of first gate members from a first layer of polysilicon, said first gate members being disposed over said first regions of said substrate and being insulated from said first regions of said substrate by said second oxide regions; forming elongated second gate members from a second layer of polysilicon, said second gate members being formed over said first gate members and being insulated from said first gate members, said second gate members being generally perpendicular to said first and said second regions of said substrate.

Claim 8

The process as in claim 5 wherein said doping step comprises the steps of: implanting an arsenic dopant into all of said second regions; implanting a phosphorous dopant into alternate ones of said second regions.

Claim 9

The process as in claim 5 wherein said second oxide regions are approximately 110 angstroms thick.

Claim 10

The process as in claim 6 wherein said second oxide regions are approximately 110 angstroms thick.

Claim 11

A process for fabricating an array of floating gate memory devices on a substrate comprising the steps of: forming elongated, spaced-apart, parallel strips of silicon nitride over first regions of said substrate, said strips of silicon nitride defining elongated, parallel, spaced-apart second regions of said substrate between said strips; doping said second regions of said substrate with an n-type dopant; covering alternate ones of said second regions of said substrate; doping the others of said n-type regions so that said others of n-type regions are more heavily doped with an n-type dopant; growing first oxide regions at said second regions of said substrate in a wet oxidation process wherein H 2 O from said wet oxidation process reacts with said strips of silicon nitride to form a compound, said compound further reacting with said substrate to form a thin silicon nitride layer disposed on the surface of said substrate in tunneling regions, said thin silicon layer inhibiting lateral growth of said first oxide regions during subsequent oxidation steps; removing said silicon nitride strips; growing second oxide regions at said first regions of said substrate, said second oxide regions being the first thermally grown silicon dioxide layer in said first regions following the removal of said silicon nitride strips; forming a plurality of first elongated polysilicon members from a first layer of polysilicon over said second oxide regions; forming elongated second gate members from a second layer of polysilicon, said second gate members being formed over said first members, said second members being generally perpendicular to said first members; etching said first elongated members in alignment with said second elongated members so as to form floating gate members disposed between said second elongated members and said substrate.

Claim 12

A process for fabricating an array of floating gate memory devices on a substrate comprising the steps of: forming elongated, spaced-apart, parallel strips of silicon nitride over first regions of said substrate, said strips of silicon nitride defining elongated, parallel, spaced-apart second regions of said substrate between said strips; doping said second regions of said substrate with an n-type dopant; covering alternate ones of said second regions of said substrate; doping the others of said n-type regions so that said others of n-type regions are more heavily doped with an n-type dopant; growing first oxide regions at said second regions of said substrate in a wet oxidation process wherein H 2 O from said wet oxidation process reacts with said strips of silicon nitride to form a compound, said compound further reacting with said substrate to form a thin silicon nitride layer disposed on the surface of said substrate in tunneling regions, said thin silicon layer inhibiting lateral growth of said first oxide regions during subsequent oxidation steps; removing said silicon nitride strips; growing second oxide regions at said first regions of said substrate, said second oxide regions being the first thermally grown silicon dioxide layer in said first regions following the removal of said silicon nitride strips; forming a plurality of first elongated polysilicon members from a first layer of polysilicon over said second oxide regions; forming elongated second gate members from a second layer of polysilicon, said second gate members being formed over said first members, said second members being generally perpendicular to said first members; etching said first elongated members in alignment with said second elongated members so as to form floating gate members disposed between said second elongated members and said substrate.

Claim 13

The process as in claim 9 wherein the first of said doping step comprises the implantation of arsenic and the second of said doping steps comprises the implantation of phosphorus.

Claim 14

The process as in claim 9 wherein said second oxide regions are approximately 110 angstroms thick.

Claim 15

The process as in claim 10 wherein said second oxide regions are approximately 110 angstroms thick.

Claim 16

The process as in any of the preceding claims in which said compound formed by the reaction of said H 2 O and said strips of silicon nitride comprises ammonia.