Layered polysilicon deposition method

Claim 1

A method of forming a multilayered polysilicon gate in an integrated circuit comprising: forming a gate silicon oxide layer over the surface of a semiconductor substrate; growing alternating layers of amorphous silicon and polysilicon overlying said gate silicon oxide layer wherein there are grown any number of alternating amorphous silicon and polysilicon layers wherein there are at least three of said polysilicon and said amorphous silicon layers all together wherein said amorphous silicon layers are formed by flowing first gases at a first temperature and wherein said polysilicon layers are formed by flowing second gases at a second temperature where said first gases are different from said second gases and said first temperature is lower than said second temperature and wherein silicon grain boundaries of said polysilicon layers are misaligned with silicon grain boundaries of said amorphous silicon layers; and etching away said amorphous silicon and said polysilicon layers not covered by a mask to form said multilayered polysilicon gate.

Claim 2

A method of forming a multilayered polysilicon gate in an integrated circuit comprising: forming a gate silicon oxide layer over the surface of a semiconductor substrate; growing alternating layers of amorphous silicon and polysilicon overlying said gate silicon oxide layer wherein there are grown any number of alternating amorphous silicon and polysilicon layers wherein there are at least three of said polysilicon and said amorphous silicon layers all together wherein said amorphous silicon layers are formed by flowing first gases at a first temperature and wherein said polysilicon layers are formed by flowing second gases at a second temperature where said first gases are different from said second gases and said first temperature is lower than said second temperature and wherein silicon grain boundaries of said polysilicon layers are misaligned with silicon grain boundaries of said amorphous silicon layers; and etching away said amorphous silicon and said polysilicon layers not covered by a mask to form said multilayered polysilicon gate.

Claim 17

A method of forming a multilayered polysilicon gate in an integrated circuit comprising: forming a gate silicon oxide layer over the surface of a semiconductor substrate; growing alternating layers of polysilicon and amorphous silicon overlying said gate silicon oxide layer growing a layer of amorphous silicon over said wherein there are grown any number of alternating amorphous silicon and polysilicon layers wherein there are at least three of said polysilicon and said amorphous silicon layers all together and wherein said amorphous silicon layers are formed by flowing Si 2 H 6 gas at a rate of between about 60 to 100 sccm and N 2 gas at a rate of between about 200 to 240 sccm at a temperature of between about 480° to 510 20 C. and wherein said polysilicon layers are formed by flowing SiH 4 gas at a rate of between about 250 to 350 sccm at a temperature of between about 620° to 650° C. and wherein silicon grain boundaries of said amorphous silicon layers are misaligned with silicon grain boundaries of said polysilicon layers; and etching away said alternating polysilicon and amorphous silicon layers not covered by a mask to form said multilayered polysilicon gate.

Claim 18

A method of forming a multilayered polysilicon gate in an integrated circuit comprising: forming a gate silicon oxide layer over the surface of a semiconductor substrate; growing alternating layers of polysilicon and amorphous silicon overlying said gate silicon oxide layer growing a layer of amorphous silicon over said wherein there are grown any number of alternating amorphous silicon and polysilicon layers wherein there are at least three of said polysilicon and said amorphous silicon layers all together and wherein said amorphous silicon layers are formed by flowing Si 2 H 6 gas at a rate of between about 60 to 100 sccm and N 2 gas at a rate of between about 200 to 240 sccm at a temperature of between about 480° to 510 20 C. and wherein said polysilicon layers are formed by flowing SiH 4 gas at a rate of between about 250 to 350 sccm at a temperature of between about 620° to 650° C. and wherein silicon grain boundaries of said amorphous silicon layers are misaligned with silicon grain boundaries of said polysilicon layers; and etching away said alternating polysilicon and amorphous silicon layers not covered by a mask to form said multilayered polysilicon gate.

Claim 29

A method of forming a multilayered polysilicon gate in an integrated circuit comprising: forming a gate silicon oxide layer over the surface of a semiconductor substrate; growing alternating layers of amorphous silicon and polysilicon overlying said gate silicon oxide layer; wherein there are grown any number of alternating amorphous silicon and polysilicon layers wherein there are at least three of said polysilicon and said amorphous silicon layers all together and wherein said amorphous silicon layers are formed by flowing Si 2 H 6 gas at a rate of between about 60 to 100 sccm and N 2 gas at a rate of between about 200 to 240 sccm at a temperature of between about 480° to 510° C. and wherein said polysilicon layers are formed by flowing SiH 4 qas at a rate of between about 250 to 350 sccm at a temperature of between about 620° to 650° C. and wherein silicon grain boundaries of said polysilicon layers are misaligned with silicon grain boundaries of said amorphous silicon layers; etching away said amorphous silicon and said polysilicon layers not covered by a mask to form said multilayered polysilicon gate; depositing a silicide layer overlying said multilayered polysilicon gate; forming source and drain regions within said semiconductor substrate; depositing an insulating layer overlying said multilayered polysilicon gate; providing contact openings through said insulating layer to said source and drain regions; depositing and patterning a conducting layer overlying said insulating layer and within said contact openings; and completing fabrication of said integrated circuit.

Claim 30

A method of forming a multilayered polysilicon gate in an integrated circuit comprising: forming a gate silicon oxide layer over the surface of a semiconductor substrate; growing alternating layers of amorphous silicon and polysilicon overlying said gate silicon oxide layer; wherein there are grown any number of alternating amorphous silicon and polysilicon layers wherein there are at least three of said polysilicon and said amorphous silicon layers all together and wherein said amorphous silicon layers are formed by flowing Si 2 H 6 gas at a rate of between about 60 to 100 sccm and N 2 gas at a rate of between about 200 to 240 sccm at a temperature of between about 480° to 510° C. and wherein said polysilicon layers are formed by flowing SiH 4 qas at a rate of between about 250 to 350 sccm at a temperature of between about 620° to 650° C. and wherein silicon grain boundaries of said polysilicon layers are misaligned with silicon grain boundaries of said amorphous silicon layers; etching away said amorphous silicon and said polysilicon layers not covered by a mask to form said multilayered polysilicon gate; depositing a silicide layer overlying said multilayered polysilicon gate; forming source and drain regions within said semiconductor substrate; depositing an insulating layer overlying said multilayered polysilicon gate; providing contact openings through said insulating layer to said source and drain regions; depositing and patterning a conducting layer overlying said insulating layer and within said contact openings; and completing fabrication of said integrated circuit.