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US5177569A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having a two layered structure gate electrode

Assignee: Renesas Electronics Corp
•
Filing: 1991-11-08
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Granted: 1993-01-05
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Expires: 2011-11-08
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Abstract

Abstract A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B + ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.

Inventors

  • 👤 Tohru Koyama
  • 👤 Katsuhiko Tamura
  • 👤 Yasuna Nakamura
  • 👤 Yoshiko Kokawa
  • 👤 Kenji Kusakabe

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 23:16
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01332; H10D64/01336; H10P; H10P14/00; H10P14/20; H10P14/24; H10P30/00; H10P30/20; H10P30/22; H10P30/222; H10P32/00; H10P32/30; H10P32/302

Claims Analysis

Total Claims: 13
Claim 1
Independent Claim 73 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type, a pair of impurity regions of a second conductivity type, formed on said semiconductor substrate of said first conductivity type with a predetermined distance therebetween, and a gate electrode formed between said pair of impurity regions above said semiconductor substrate with an insulating film thereunder, said gate electrode comprising a multilayer structure of a polycrystal layer and a single crystal layer.
Claim 2
Dependent Claim 73 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type, a pair of impurity regions of a second conductivity type, formed on said semiconductor substrate of said first conductivity type with a predetermined distance therebetween, and a gate electrode formed between said pair of impurity regions above said semiconductor substrate with an insulating film thereunder, said gate electrode comprising a multilayer structure of a polycrystal layer and a single crystal layer.
Claim 3
Dependent Claim 27 words
The semiconductor device according to claim 1, wherein said polycrystal layer comprises a polycrystal silicon layer, and said single crystal layer comprises a single crystal silicon layer.
Claim 4
Dependent Claim 18 words
The semiconductor device according to claim 2, wherein said polycrystal silicon layer comprises a CVD polycrystal silicon layer.
Claim 5
Dependent Claim 20 words
The semiconductor device according to claim 2, wherein said single crystal silicon layer comprises an epitaxial single crystal silicon layer.
Claim 6
Dependent Claim 110 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type, a pair of impurity regions of a second conductivity type, formed on said semiconductor substrate of said first conductivity type with a predetermined distance therebetween, and a gate electrode formed between said pair of impurity regions above said semiconductor substrate with an insulating film thereunder, wherein said gate electrode comprises a polycrystal layer formed on said insulating film on said semiconductor substrate, and having the crystal orientation of the crystal grain thereof arranged in a predetermined orientation, a single crystal layer formed on said polycrystal layer, and having a crystal orientation identical to that of said polycrystal layer.
Claim 7
Dependent Claim 110 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type, a pair of impurity regions of a second conductivity type, formed on said semiconductor substrate of said first conductivity type with a predetermined distance therebetween, and a gate electrode formed between said pair of impurity regions above said semiconductor substrate with an insulating film thereunder, wherein said gate electrode comprises a polycrystal layer formed on said insulating film on said semiconductor substrate, and having the crystal orientation of the crystal grain thereof arranged in a predetermined orientation, a single crystal layer formed on said polycrystal layer, and having a crystal orientation identical to that of said polycrystal layer.
Claim 8
Dependent Claim 27 words
The semiconductor device according to claim 5, wherein said polycrystal layer comprises a polycrystal silicon layer and said single crystal layer comprises a single crystal silicon layer.
Claim 9
Dependent Claim 28 words
The semiconductor device according to claim 6, wherein the crystal orientation of said polycrystal silicon layer and said single crystal silicon layer is a plane orientation of 110.
Claim 10
Dependent Claim 28 words
The semiconductor device according to claim 6, wherein the crystal orientation of said polycrystal silicon layer and said single crystal silicon layer is a plane orientation of 111.
Claim 11
Dependent Claim 18 words
The semiconductor device according to claim 6, wherein said polycrystal silicon layer comprises a CVD polycrystal silicon layer.
Claim 12
Dependent Claim 20 words
The semiconductor device according to claim 6, wherein said single crystal silicon layer comprises an epitaxial single crystal silicon layer.
Claim 13
Dependent Claim 21 words
The semiconductor device according to claim 5, wherein said gate electrode and said pair of impurity regions implement a MOS transistor.

References Cited (Backward Citations)

US4808555A Cited
US4897368A Cited
JPH01220438A Cited
JPH02140933A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1996-01-05 1996-07-06 1997-01-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2000-01-05 2000-07-06 2001-01-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2004-01-05 2004-07-06 2005-01-05 $7700.00 Window Closed / Lapsed

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