Oxidation method for removing fluorine gas inside polysilicon during semiconductor manufacturing to prevent delamination of subsequent layer induced by fluorine outgassing dielectric

Claim 1

A method for manufacturing integrated circuit semiconductor device which comprises said steps of: providing a semiconductor substrate with an N-well therein, forming a field oxide and a gate oxide layer on said N-well, forming a blanket polysilicon layer over said field oxide and said gate oxide layer and patterning said polysilicon layer to form a polysilicon gate electrode, forming a blanket sacrificial silicon oxide layer over said polysilicon gate electrode and over said gate oxide layer, ion implanting boron difluoride 49 (BF 2 ) + ions into said polysilicon gate electrode and into said N-well self-aligned with said polysilicon gate electrode and to dope said polysilicon gate electrode with P-type dopant thereby forming doped regions in said N-well and in said polysilicon gate electrode, said boron fluoride 49 (BF 2 ) + dopant is ion implanted at an energy from about 60 keV to about 80 keV and a dose from about 1 E 15 ion/cm 2 to about 5 E 15 ions/cm 2 , said sacrificial silicon oxide layer preventing delamination of subsequent dielectric layers by removing fluorine gas from said polysilicon gate electrode, etching said blanket sacrificial silicon oxide layer away from said device, after etching said blanket sacrificial silicon oxide layer away from said device, forming a dielectric structure over said device by the steps as follows: form a first layer comprising a polyoxide layer on said polysilicon gate electrode, form a second layer comprising a blanket silicon nitride layer on said device covering said first layer, form a third layer comprising a blanket silicon oxide layer composed of O 3 -TEOS material on said device covering said second layer, and form a fourth layer comprising a blanket BPSG layer on said device covering said third layer.

Claim 2

A method for manufacturing integrated circuit semiconductor device which comprises said steps of: providing a semiconductor substrate with an N-well therein, forming a field oxide and a gate oxide layer on said N-well, forming a blanket polysilicon layer over said field oxide and said gate oxide layer and patterning said polysilicon layer to form a polysilicon gate electrode, forming a blanket sacrificial silicon oxide layer over said polysilicon gate electrode and over said gate oxide layer, ion implanting boron difluoride 49 (BF 2 ) + ions into said polysilicon gate electrode and into said N-well self-aligned with said polysilicon gate electrode and to dope said polysilicon gate electrode with P-type dopant thereby forming doped regions in said N-well and in said polysilicon gate electrode, said boron fluoride 49 (BF 2 ) + dopant is ion implanted at an energy from about 60 keV to about 80 keV and a dose from about 1 E 15 ion/cm 2 to about 5 E 15 ions/cm 2 , said sacrificial silicon oxide layer preventing delamination of subsequent dielectric layers by removing fluorine gas from said polysilicon gate electrode, etching said blanket sacrificial silicon oxide layer away from said device, after etching said blanket sacrificial silicon oxide layer away from said device, forming a dielectric structure over said device by the steps as follows: form a first layer comprising a polyoxide layer on said polysilicon gate electrode, form a second layer comprising a blanket silicon nitride layer on said device covering said first layer, form a third layer comprising a blanket silicon oxide layer composed of O 3 -TEOS material on said device covering said second layer, and form a fourth layer comprising a blanket BPSG layer on said device covering said third layer.