Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron mosfets

Claim 1

A method of forming an elevated source/drain structure in the manufacture of an integrated circuit comprising: providing a semiconductor substrate having active areas separated by isolation areas wherein there is an n-channel active area and a p-channel active area; providing a gate oxide layer over the surface of said semiconductor substrate; depositing a layer of polysilicon overlying said gate oxide layer and patterning said polysilicon layer to form a gate electrodes over each of said active areas; oxidizing said polysilicon layer remaining to form a silicon oxide layer over all surfaces of said gate electrodes; forming first spacers on sidewalls of said gate electrodes wherein said first spacers have a first dopant concentration; forming a first mask over said n-channel active area; removing said first spacers in said p-channel active area; forming second spacers on the sidewalls of said gate electrodes in said p-channel active area wherein said second spacers have a second dopant concentration different from said first dopant concentration; removing said first mask; growing an epitaxial layer on the surface of said semiconductor substrate wherein said epitaxial layer forms said elevated source/drain structure; forming a second mask over said p-channel active area; implanting first ions into said n-channel active area; removing said second mask; forming a third mask over said n-channel active area; implanting second ions into said p-channel active area; removing said third mask; and driving in said first and second ions to form heavily doped regions within said semiconductor substrate underlying said elevated source/drain structure in the fabrication of said integrated circuit.

Claim 2

A method of forming an elevated source/drain structure in the manufacture of an integrated circuit comprising: providing a semiconductor substrate having active areas separated by isolation areas wherein there is an n-channel active area and a p-channel active area; providing a gate oxide layer over the surface of said semiconductor substrate; depositing a layer of polysilicon overlying said gate oxide layer and patterning said polysilicon layer to form a gate electrodes over each of said active areas; oxidizing said polysilicon layer remaining to form a silicon oxide layer over all surfaces of said gate electrodes; forming first spacers on sidewalls of said gate electrodes wherein said first spacers have a first dopant concentration; forming a first mask over said n-channel active area; removing said first spacers in said p-channel active area; forming second spacers on the sidewalls of said gate electrodes in said p-channel active area wherein said second spacers have a second dopant concentration different from said first dopant concentration; removing said first mask; growing an epitaxial layer on the surface of said semiconductor substrate wherein said epitaxial layer forms said elevated source/drain structure; forming a second mask over said p-channel active area; implanting first ions into said n-channel active area; removing said second mask; forming a third mask over said n-channel active area; implanting second ions into said p-channel active area; removing said third mask; and driving in said first and second ions to form heavily doped regions within said semiconductor substrate underlying said elevated source/drain structure in the fabrication of said integrated circuit.

Claim 13

A method of forming an elevated source/drain structure with solid-phase diffused source/drain extensions in the manufacture of an integrated circuit comprising: providing a semiconductor substrate having active areas separated by isolation areas wherein there is an n-channel active area and a p-channel active area; providing a gate oxide layer over the surface of said semiconductor substrate; depositing a layer of polysilicon overlying said gate oxide layer and patterning said polysilicon layer to form a gate electrodes over each of said active areas; oxidizing said polysilicon layer remaining to form a silicon oxide layer over all surfaces of said gate electrodes; forming first spacers on sidewalls of said gate electrodes wherein said first spacers have a first dopant concentration; forming a first mask over said n-channel active area; removing said first spacers in said p-channel active area; forming second spacers on the sidewalls of said gate electrodes in said p-channel active area wherein said second spacers have a second dopant concentration different from said first dopant concentration; removing said first mask; growing an epitaxial layer on the surface of said semiconductor substrate wherein said epitaxial layer forms said elevated source/drain structure; forming a second mask over said p-channel active area; implanting first ions into said n-channel active area; removing said second mask; forming a third mask over said n-channel active area; implanting second ions into said p-channel active area; removing said third mask; driving in said first and second ions to form heavily doped regions within said semiconductor substrate underlying said elevated source/drain structure wherein said driving in also drives in said first and second dopant concentrations of said first and second spacers to form source/drain extensions within said n-channel and p-channel active areas underlying said first and second spacers to complete the formation of said elevated source/drain structure with solid-phase diffused source/drain extensions in the manufacture of an integrated circuit; and forming a contact layer on said elevated source/drain structure.

Claim 14

A method of forming an elevated source/drain structure with solid-phase diffused source/drain extensions in the manufacture of an integrated circuit comprising: providing a semiconductor substrate having active areas separated by isolation areas wherein there is an n-channel active area and a p-channel active area; providing a gate oxide layer over the surface of said semiconductor substrate; depositing a layer of polysilicon overlying said gate oxide layer and patterning said polysilicon layer to form a gate electrodes over each of said active areas; oxidizing said polysilicon layer remaining to form a silicon oxide layer over all surfaces of said gate electrodes; forming first spacers on sidewalls of said gate electrodes wherein said first spacers have a first dopant concentration; forming a first mask over said n-channel active area; removing said first spacers in said p-channel active area; forming second spacers on the sidewalls of said gate electrodes in said p-channel active area wherein said second spacers have a second dopant concentration different from said first dopant concentration; removing said first mask; growing an epitaxial layer on the surface of said semiconductor substrate wherein said epitaxial layer forms said elevated source/drain structure; forming a second mask over said p-channel active area; implanting first ions into said n-channel active area; removing said second mask; forming a third mask over said n-channel active area; implanting second ions into said p-channel active area; removing said third mask; driving in said first and second ions to form heavily doped regions within said semiconductor substrate underlying said elevated source/drain structure wherein said driving in also drives in said first and second dopant concentrations of said first and second spacers to form source/drain extensions within said n-channel and p-channel active areas underlying said first and second spacers to complete the formation of said elevated source/drain structure with solid-phase diffused source/drain extensions in the manufacture of an integrated circuit; and forming a contact layer on said elevated source/drain structure.