High performance sub-micron p-channel transistor with germanium implant

Claim 1

Method of forming semiconductor circuit devices which include, as a part of each device, a plurality of cells, said cells including active circuit elements, including p channel transistors, to control signals, the method comprising: a) preparing a silicon wafer and establishing the wafer as a substrate, and forming an oxide layer on the substrate; b) forming a nitride layer on the wafer to define field oxide and active areas; c) forming a pattern of nitride from said nitride layer over selected portions of the active areas; d) implanting the oxide layer adjacent the nitride pattern with an implant dopant which functions as a channel stop for isolating parasitic field effect transistors; e) growing oxide on the substrate around the nitride pattern, using LOCOS techniques; f) removing the nitride pattern; g) removing a portion of the oxide such that a fraction of the oxide in active areas formerly under the nitride pattern is removed, said removed portion defining channels for p channel transistors; h) implanting germanium into said channel areas of the substrate through the active areas from which a fraction of the oxide has been removed; i) growing further oxide over the germanium-implanted wafer; j) implanting boron through said further oxide; k) stripping said further oxide; l) growing a gate oxide layer over the active areas; m) depositing a first conductive layer over the gate oxide layer and etching the conductive layer to leave conductive material from the conductive layer in a gate pattern; n) implanting lightly doped source/drain regions around the gate pattern; o) forming oxide spacers adjacent to the conductive material in the gate pattern; and p) implanting source and drain impurities to form P+ source and drain regions adjacent to the gate pattern, separated by P- regions immediately adjacent to the gate pattern.