CMOS process flow with small gate geometry LDO N-channel transistors

Claim 2

A process for forming a lightly doped drain (LDD) in a complementary MOS circuit, comprising the sequential steps of: forming a first gate for a first MOS device on a first area of first conductivity type of an integrated circuit substrate, and forming a second gate for a second MOS device on a second area of second conductivity type of the substrate; selectively forming a barrier material over the first and second gates; implanting a lightly doped material of the first conductivity type into an upper surface of the first and second areas of the substrate adjacent to but not beneath the first and second gates; forming a first disposable barrier material over selected areas of the substrate including the second gate and excluding the first gate; implanting heavily doped source/drain regions along side edges of the first gate while the second gate is protected by the first disposable barrier material; removing the first disposable barrier material from over the selected areas of the substrate; forming oxide sidewall spacers along side edges of the first and second gates; forming a second disposable barrier material over selected areas of the substrate including the first gate and excluding the second gate; implanting heavily doped source/drain regions along oxide sidewall spacer edges of the second gate; and removing the second disposable barrier material from over the selected areas of the substrate.

Claim 3

The process of claim 1 wherein the first conductivity type is P conductivity and the second conductivity type is N conductivity.

Claim 4

A process for forming lightly doped drains (LDDs) in N-channel transistors only in a CMOS circuit, comprising the sequential steps of: forming a first gate for a P-channel transistor on a first area of first conductivity type of an integrated circuit substrate, and forming a second gate for an N-channel transistor on a second area of second conductivity type of the substrate; selectively forming a barrier material over the first and second gates; implanting a lightly doped material of N conductivity into an upper surface of the first and second areas of the substrate adjacent to but not beneath the first and second gates; forming a first photoresist mask over selected areas of the substrate including the second gate and excluding the first gate; implanting heavily doped P conductivity source/drain regions along side edges of the first gate while the second gate is protected by the first disposable barrier material to form the P-channel transistor; removing the first photoresist mask from over the selected areas of the substrate; forming oxide sidewall spacers along side edges of the first and second gates; forming a second photoresist mask over selected areas of the substrate including the first gate and excluding the second gate; implanting heavily doped N conductivity source/drain regions along oxide sidewall spacer edges of the second gate to form the N-channel transistor; and removing the second photoresist mask from over the selected areas of the substrate.

Claim 5

A process for forming lightly doped drains (LDDs) in N-channel transistors only in a CMOS circuit, comprising the sequential steps of: forming a first gate for a P-channel transistor on a first area of first conductivity type of an integrated circuit substrate, and forming a second gate for an N-channel transistor on a second area of second conductivity type of the substrate; selectively forming a barrier material over the first and second gates; implanting a lightly doped material of N conductivity into an upper surface of the first and second areas of the substrate adjacent to but not beneath the first and second gates; forming a first photoresist mask over selected areas of the substrate including the second gate and excluding the first gate; implanting heavily doped P conductivity source/drain regions along side edges of the first gate while the second gate is protected by the first disposable barrier material to form the P-channel transistor; removing the first photoresist mask from over the selected areas of the substrate; forming oxide sidewall spacers along side edges of the first and second gates; forming a second photoresist mask over selected areas of the substrate including the first gate and excluding the second gate; implanting heavily doped N conductivity source/drain regions along oxide sidewall spacer edges of the second gate to form the N-channel transistor; and removing the second photoresist mask from over the selected areas of the substrate.