CMOS process for fabricating integrated circuits, particularly dynamic memory cells with storage capacitors

Claim 1

A process for fabricating complementary metal-oxide-semiconductor dynamic memory comprising the steps of: forming a well of a first conductivity type in an epitaxial layer; forming an oxide layer of a first thickness on said epitaxial layer; forming field oxide regions on said oxide layer to a second thickness; defining first regions in said well for capacitors by performing a wet etch to remove said oxide layer in said first region and reduce said field oxide regions in said first region to a third thickness; non-implanting said defined first regions with a dopant of a second conductivity type; forming an insulative layer at least over said defined first regions; forming a first polysilicon layer over said well, said first polysilicon layer being used to form a portion of said capacitor; forming openings in said first polysilicon layer to define second regions for field effect transistors which are coupled to said capacitors; forming word lines from a second layer of polysilicon; whereby memory cells are fabricated in said well and the area for capacitor formation is increased.