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US4044454A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming integrated circuit regions defined by recessed dielectric isolation

Assignee: International Business Machines Corp
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Filing: 1975-04-16
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Granted: 1977-08-30
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Expires: 1995-04-16
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Abstract

Abstract In the fabrication of integrated circuits, a method is provided for forming dielectrically isolated regions in a silicon substrate comprising initially introducing conductivity-determining impurities into the substrate to form at least one region of one-type conductivity at the surface of said substrate. Then, a mask comprising a composite of a bottom layer of silicon dioxide and a top layer of silicon nitride is formed over at least a portion of the surface of said introduced regions. The substrate is then subsequently thermally oxidized to an extent sufficient to form regions of recessed silicon dioxide abutting and thus laterally defining said region of one-type conductivity. In this manner, it is ensured that the recessed silicon dioxide will abut introduced region irrespective of the extent of the "bird's beak" normally associated with thermal oxidation utilizing silicon dioxide-silicon nitride masking.

Inventors

  • 👤 Ingrid E. Magdo

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 22:02
CPC Classifications
H; H10; H10P; H10P95/00; H10P14/00; H10P14/60; H10P14/61; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/10; H10W10/13; H10W20/00; H10W20/40; Y; Y10; Y10S; Y10S148/00; Y10S148/036; Y10S148/049; Y10S148/051; Y10S148/082; Y10S148/085; Y10S148/117

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 245 words
In the fabrication of integrated circuits, a method for forming dielectrically isolated regions in a silicon substrate comprising introducing conductivity-determining impurities into the substrate to form at least one region of one-type conductivity at the surface of said substrate forming over at least a part of said surface of said region, a composite mask comprising a lower layer of silicon dioxide in contact with said surface, and an upper layer of silicon nitride on said lower layer, said mask having a plurality of apertures extending therethrough, etching recesses in the portions of said substrate exposed in said apertures, thermally oxidizing the recessed portions of said substrate to an extent sufficient to form regions of recessed silicon dioxide abutting and laterally defining said at least one region of one-type conductivity, said mask acting as a barrier to prevent oxidation of the unrecessed surface of said substrate, providing a layer of electrically insulative material over at least a portion of the surface of said substrate by a processing step comprising at least the removal of said silicon nitride layer, forming at least one contact opening through said electrically insulative layer to expose at least a portion of said at least one region of one-type conductivity, said contact opening exposing a portion of a region of recessed silicon dioxide abutting said one-type conductivity region and depositing metal in said contact opening to form a contact to said region of one-type conductivity, said contact over-lapping said recessed silicon dioxide.
Claim 2
Dependent Claim 245 words
In the fabrication of integrated circuits, a method for forming dielectrically isolated regions in a silicon substrate comprising introducing conductivity-determining impurities into the substrate to form at least one region of one-type conductivity at the surface of said substrate forming over at least a part of said surface of said region, a composite mask comprising a lower layer of silicon dioxide in contact with said surface, and an upper layer of silicon nitride on said lower layer, said mask having a plurality of apertures extending therethrough, etching recesses in the portions of said substrate exposed in said apertures, thermally oxidizing the recessed portions of said substrate to an extent sufficient to form regions of recessed silicon dioxide abutting and laterally defining said at least one region of one-type conductivity, said mask acting as a barrier to prevent oxidation of the unrecessed surface of said substrate, providing a layer of electrically insulative material over at least a portion of the surface of said substrate by a processing step comprising at least the removal of said silicon nitride layer, forming at least one contact opening through said electrically insulative layer to expose at least a portion of said at least one region of one-type conductivity, said contact opening exposing a portion of a region of recessed silicon dioxide abutting said one-type conductivity region and depositing metal in said contact opening to form a contact to said region of one-type conductivity, said contact over-lapping said recessed silicon dioxide.
Claim 3
Dependent Claim 13 words
The method of claim 1 wherein said conductivity-determining impurities are introduced by diffusion.
Claim 4
Dependent Claim 14 words
The method of claim 1 wherein said conductivity-determining impurities are introduced by ion implantation.
Claim 5
Dependent Claim 62 words
The method of claim 1 wherein said conductivity-determining impurities are introduced so that said region of one-type conductivity blankets the surface of said substrate, and said regions of recessed silicon dioxide are formed so as to laterally separate said blanket region of one-type conductivity into a plurality of regions of said one-type conductivity, each laterally defined by said recessed silicon dioxide regions.
Claim 6
Dependent Claim 25 words
The method of claim 4 wherein said recesses are etched into said substrate to a depth beyond that of said blanket region of one-type conductivity.
Claim 7
Dependent Claim 35 words
The method of claim 1 wherein said contact opening is formed so as to completely traverse defined region of one-type conductivity and to overlap said recessed oxide regions on both sides of said traversed region.

References Cited (Backward Citations)

US3755001A Cited
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US3900350A Cited
US3808058A Cited
US3853633A Cited
US3933540A Cited
US3962779A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1980-08-29 1981-02-28 1981-08-30 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1984-08-29 1985-02-28 1985-08-30 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1988-08-29 1989-02-28 1989-08-30 $7700.00 Window Closed / Lapsed

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