US3962779A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating oxide isolated integrated circuits
Assignee: AT&T Inc
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Filing: 1974-12-23
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Granted: 1976-06-15
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Expires: 1994-12-23
Abstract
Abstract A method of making an oxide isolated integrated circuit structure is simplified by forming a first level metallization pattern without the conventional underlying insulating layer and without the need for restricting the size of the metallization to the size of the semiconductor regions to be contacted. Portions of the first level metallization pattern can extend on the oxide isolation region to contact two otherwise isolated semiconductor zones. Additionally, subsequent to the formation of the oxide isolation regions and the first level metallization, an intermediate dielectric masking pattern is formed so the combination of the first level metallization, the oxide isolation regions and the masking pattern defines zones for the introduction of impurities. Further, the masking pattern alone is used to provide contact holes for a subsequently formed second level metallization pattern.
Inventors
- 👤 Roger Edwards
- 👤 William Joshua Evans
- 👤 Wesley Norman Grant
- 👤 Bernard Thomas Murphy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 23:14
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/10; H10W10/13; H10W20/00; H10W20/40; Y; Y10; Y10S; Y10S148/00; Y10S148/02; Y10S148/053; Y10S148/085; Y10S148/116; Y10S148/117; Y10S438/00; Y10S438/98
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
151 words
A method for fabricating a semiconductive integrated circuit comprising the steps of preparing a semiconductive element which includes on one surface a plurality of semiconductive regions which are separated at such surface by dielectric isolation regions, forming directly on said surface a first metallization pattern, depositing an insulating layer over said surface including the first metallization pattern, forming openings in the insulating layer for exposing at least one portion of said first metallization pattern and a portion of at least one semiconductive region, introducing impurities into the exposed portions of said semiconductive region for affecting their conductivities, and forming over said surface, including the first metallization pattern and the insulating layer, a second metallization pattern without reforming the openings in said insulating layer, said second metallization pattern making electrical connection to the exposed portions of the semiconductive regions and of the first metallization pattern through the openings in the insulating layer.
Claim 2
Independent Claim
151 words
A method for fabricating a semiconductive integrated circuit comprising the steps of preparing a semiconductive element which includes on one surface a plurality of semiconductive regions which are separated at such surface by dielectric isolation regions, forming directly on said surface a first metallization pattern, depositing an insulating layer over said surface including the first metallization pattern, forming openings in the insulating layer for exposing at least one portion of said first metallization pattern and a portion of at least one semiconductive region, introducing impurities into the exposed portions of said semiconductive region for affecting their conductivities, and forming over said surface, including the first metallization pattern and the insulating layer, a second metallization pattern without reforming the openings in said insulating layer, said second metallization pattern making electrical connection to the exposed portions of the semiconductive regions and of the first metallization pattern through the openings in the insulating layer.
Claim 3
Independent Claim
168 words
A method for fabricating a semiconductive integrated circuit comprising the steps of preparing a semiconductive element which includes on one surface a plurality of semiconductive regions which are separated at said surface by dielectric isolation regions, forming on said surface a first metallization pattern comprising a plurality of discrete conductive segments, at least one of which overlies and is contiguous with both dielectric and semiconductive regions, depositing an insulating layer over said surface including the first metallization pattern, forming openings in the insulating layer for exposing a portion of said conductive segments and a portion of at least one semiconductive region, introducing impurities into the exposed portions of said semiconductive regions for affecting their conductivities, and forming over said surface, including the first metallization pattern and the insulating layer, a second metallization pattern comprising a plurality of conductive segments at least one of which contacts the exposed portion of a semiconductive region and at least one of which contacts an exposed conductive segment of the first metallization pattern.
Claim 4
Independent Claim
168 words
A method for fabricating a semiconductive integrated circuit comprising the steps of preparing a semiconductive element which includes on one surface a plurality of semiconductive regions which are separated at said surface by dielectric isolation regions, forming on said surface a first metallization pattern comprising a plurality of discrete conductive segments, at least one of which overlies and is contiguous with both dielectric and semiconductive regions, depositing an insulating layer over said surface including the first metallization pattern, forming openings in the insulating layer for exposing a portion of said conductive segments and a portion of at least one semiconductive region, introducing impurities into the exposed portions of said semiconductive regions for affecting their conductivities, and forming over said surface, including the first metallization pattern and the insulating layer, a second metallization pattern comprising a plurality of conductive segments at least one of which contacts the exposed portion of a semiconductive region and at least one of which contacts an exposed conductive segment of the first metallization pattern.
Claim 5
Dependent Claim
28 words
The method of claim 2 in which the first metallization pattern includes at least one conductive segment which interconnects two semiconductive regions separated by a dielectric isolation region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-15 | 1979-12-15 | 1980-06-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-15 | 1983-12-15 | 1984-06-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-15 | 1987-12-15 | 1988-06-15 | $7700.00 | Window Closed / Lapsed |