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US3961999A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for forming recessed dielectric isolation with a minimized "bird's beak" problem

Assignee: International Business Machines Corp
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Filing: 1975-06-30
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Granted: 1976-06-08
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Expires: 1995-06-30
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Abstract

Abstract In the fabrication of integrated circuits, a method is provided for forming recessed silicon dioxide isolation in integrated circuits in which the "bird's beak" problems associated with conventional silicon dioxide-silicon nitride composite masking structures is minimized. A conventional composite mask comprising a bottom layer of silicon dioxide and an upper layer of silicon nitride having a plurality of openings defining the regions in the silicon substrate which are to be thermally oxidized is formed on a silicon substrate. Recesses are then etched in the silicon substrate in registration with the openings in the composite mask. Then, the silicon dioxide layer is, in effect, over-etched to extend the openings in the silicon dioxide to greater lateral dimensions than the openings in the silicon nitride layer whereby the silicon nitride at the periphery of the openings is undercut. A layer of silicon is then deposited in the recesses covering the undercut portions of said silicon nitride layer. Then, the structure subjected to thermal oxidation whereby the silicon in and abutting the recesses is oxidized to form regions of recessed silicon dioxide substantially coplanar with the unrecessed portions of the silicon substrate. Because of the undercutting and the deposition of silicon in the recesses, the "bird's beak" effect is minimized.

Inventors

  • 👤 Igor Antipov

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 21:30
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10P; H10P95/00; H10W10/01; H10W10/011; H10W10/014; H10W10/0142; Y; Y10; Y10S; Y10S148/00; Y10S148/043; Y10S148/085; Y10S148/114; Y10S148/117; Y10S148/122; Y10S148/151; Y10S438/00; Y10S438/969

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 169 words
In the fabrication of integrated circuits, a method for forming dielectrically isolated regions in a silicon substrate comprising forming a layer of silicon dioxide on a surface of the substrate, forming a masking layer of silicon nitride having a plurality of openings on said silicon dioxide layer etching a plurality of openings through the masked silicon dioxide layer in registration with and having greater lateral dimensions than the silicon nitride mask openings, whereby said silicon dioxide layer openings undercut and expose the underside of the silicon nitride layer at the periphery of said silicon dioxide layer openings etching a plurality of recesses in the silicon substrate respectively in registration with the openings through the silicon dioxide and silicon nitride layers, depositing a layer of silicon to at least partially fill said recesses and cover said exposed underside of said silicon nitride layer, and thermally oxidizing the silicon in and abutting said recesses to form regions of recessed silicon dioxide substantially coplanar with the unrecessed portions of the silicon substrate.
Claim 2
Dependent Claim 169 words
In the fabrication of integrated circuits, a method for forming dielectrically isolated regions in a silicon substrate comprising forming a layer of silicon dioxide on a surface of the substrate, forming a masking layer of silicon nitride having a plurality of openings on said silicon dioxide layer etching a plurality of openings through the masked silicon dioxide layer in registration with and having greater lateral dimensions than the silicon nitride mask openings, whereby said silicon dioxide layer openings undercut and expose the underside of the silicon nitride layer at the periphery of said silicon dioxide layer openings etching a plurality of recesses in the silicon substrate respectively in registration with the openings through the silicon dioxide and silicon nitride layers, depositing a layer of silicon to at least partially fill said recesses and cover said exposed underside of said silicon nitride layer, and thermally oxidizing the silicon in and abutting said recesses to form regions of recessed silicon dioxide substantially coplanar with the unrecessed portions of the silicon substrate.
Claim 3
Dependent Claim 67 words
The method of claim 1 wherein the openings initially etched through said masked silicon dioxide layer have substantially the same lateral dimensions as said silicon nitride mask openings, and subsequent to the etching of said plurality of said recesses in said substrate, said silicon dioxide layer is further etched to extend the lateral dimensions of the openings in said silicon dioxide layer to undercut said silicon nitride.
Claim 4
Dependent Claim 22 words
The method of claim 2 wherein said extended openings through said silicon dioxide layer also have greater lateral dimensions than said recesses.
Claim 5
Dependent Claim 22 words
The method of claim 3 wherein said deposited layer of silicon is formed by chemical vapor deposition to partially fill said recesses.
Claim 6
Dependent Claim 43 words
The method of claim 3 wherein said silicon is blanket deposited in said recesses and over said silicon nitride mask, whereby both the silicon deposited in the recesses and on the silicon nitride mask is oxidized to silicon dioxide during said thermal oxidation.

References Cited (Backward Citations)

US3783047A Cited
US3900350A Cited
US3858231A Cited
US3886000A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-06-08 1979-12-08 1980-06-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-06-08 1983-12-08 1984-06-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-06-08 1987-12-08 1988-06-08 $7700.00 Window Closed / Lapsed

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