US4364075A
Expired / Lapsed
US
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CMOS Dynamic RAM cell and method of fabrication
Assignee: Intel Corp
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Filing: 1980-09-02
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Granted: 1982-12-14
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Expires: 2000-09-02
Abstract
Abstract A high density CMOS dynamic RAM cell comprising a transistor and capacitance means formed in an n-well is disclosed. The capacitance means includes a polysilicon plate member disposed above a p-type region formed in the n-well. A buried contact, extending from the plate member, pierces the p-type region and contacts the well. In addition to the capacitance associated with the plate member, p-type region and well, capacitance is obtained between the side walls of the n-type regions and p-type regions.
Inventors
- 👤 Mark T. Bohr
- 👤 Kenneth K. Yu
- 👤 Ronald J. C. Chwang
- 👤 Neil C. Berglund
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 07:27
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C5/00; G11C5/005; H10W; H10W42/00; H10W42/20; H10W42/25
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
102 words
A metal-oxide-semiconductor, dynamic memory cell, disposed in an n-type well on a p-type silicon substrate comprising: a transistor; a capacitor coupled to said transistor for storing charge comprising: a plate member disposed above said well with an insulating layer disposed between said plate member and said well; a p-type region disposed within said well below said plate member; an n-type buried contact region disposed within said p-type region, said n-type region extending into said well for coupling said plate member to said well; whereby a high density dynamic memory cell is realized which has high immunity to failures associated with alpha particles.
Claim 2
Dependent Claim
102 words
A metal-oxide-semiconductor, dynamic memory cell, disposed in an n-type well on a p-type silicon substrate comprising: a transistor; a capacitor coupled to said transistor for storing charge comprising: a plate member disposed above said well with an insulating layer disposed between said plate member and said well; a p-type region disposed within said well below said plate member; an n-type buried contact region disposed within said p-type region, said n-type region extending into said well for coupling said plate member to said well; whereby a high density dynamic memory cell is realized which has high immunity to failures associated with alpha particles.
Claim 3
Dependent Claim
14 words
The cell defined by claim 1 wherein said plate member is a polysilicon member.
Claim 4
Dependent Claim
15 words
The cell defined by claim 2 wherein said polysilicon member contact said buried contact region.
Claim 5
Dependent Claim
19 words
The cell defined by claim 3 wherein said p-type region is contiguous with a source/drain region of said transistor.
Claim 6
Dependent Claim
20 words
The cell defined by claim 3 wherein said polysilicon member and buried contact region are shared with an adjacent cell.
Claim 7
Dependent Claim
122 words
A pair of CMOS dynamic memory cells found in an n-type well comprising: a first and second p-channel transistor; a p-type region disposed in said well; an n-type region disposed through said p-type region into contact with said well, separating said p-type region into a first and a second p-type region; said first region being coupled to said first transistor and said second region being coupled to said second transistor; a plate member disposed over said p-type region, said member contacting said n-type region; whereby said plate member along with said first and second regions form capacitance storage means for said cells, and wherein additional storage capacitance is formed by the junctions between said n-type region and said first and second regions.
Claim 8
Dependent Claim
122 words
A pair of CMOS dynamic memory cells found in an n-type well comprising: a first and second p-channel transistor; a p-type region disposed in said well; an n-type region disposed through said p-type region into contact with said well, separating said p-type region into a first and a second p-type region; said first region being coupled to said first transistor and said second region being coupled to said second transistor; a plate member disposed over said p-type region, said member contacting said n-type region; whereby said plate member along with said first and second regions form capacitance storage means for said cells, and wherein additional storage capacitance is formed by the junctions between said n-type region and said first and second regions.
Claim 9
Dependent Claim
14 words
The cells defined by claim 6 wherein said plate member is a polysilicon member.
Claim 10
Dependent Claim
15 words
The cells defined by claim 7 wherein said p-type region is a boron doped region.
References Cited (Backward Citations)
US4158238A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-12-13 | 1986-06-14 | 1986-12-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-12-13 | 1990-06-14 | 1990-12-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-12-13 | 1994-06-14 | 1994-12-14 | $7700.00 | Window Closed / Lapsed |