US4432006A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1980-08-29
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Granted: 1984-02-14
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Expires: 2000-08-29
Abstract
Abstract In a semiconductor memory device of the present, due to a heavily doped region formed on the semiconductor substrate, the depletion layer does not spread deeply toward the interior of the semiconductor substrate. In addition, a capacitor is formed by the heavily doped region, an insulating film formed on this region and a semiconductor layer formed on this insulating film. As a result, variation of capacitance of the capacitor due to α-ray particles is low. Furthermore, information is stored in the semiconductor layer which is formed above the semiconductor substrate so that the occurrence of a soft error is minimized.
Inventors
- 👤 Akira Takei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 00:39
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/005; H; H10; H10B; H10B12/00; H10B12/30; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D62/00; H10D62/60; H10W; H10W42/00; H10W42/20; H10W42/25
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
248 words
A semiconductor memory device comprising: a semiconductor substrate having a first conductivity type and first and second surface regions that are separated from each other; a heavily doped region having said first conductivity type formed in said first surface region of said semiconductor substrate; a first insulating film formed on said heavily doped region over said first surface region of said semiconductor substrate and leaving exposed said second surface region of said semiconductor substrate; a semiconductor layer, including a first part formed on said first insulating film over said first surface region, and a second part formed on said semiconductor substrate in said second surface region, said second part including a single-crystalline region where said second part of said semiconductor layer contacts said semiconductor substrate in said second surface region; a capacitor comprising (a) at least a part of said first insulating film over said first surface region of said semiconductor substrate, (b) at least a part of said heavily doped region in said first surface region of said semiconductor substrate, and (c) said first part of said semiconductor layer which is disposed on said first insulating film over said first surface region of said substrate, said first part of said semiconductor layer over said first surface region comprising an information storage region; and said second part of said semiconductor layer comprising the source, channel and drain regions of a transistor, said source region being short-circuited with said first part of the semiconductor layer comprised in said capacitor.
Claim 2
Dependent Claim
248 words
A semiconductor memory device comprising: a semiconductor substrate having a first conductivity type and first and second surface regions that are separated from each other; a heavily doped region having said first conductivity type formed in said first surface region of said semiconductor substrate; a first insulating film formed on said heavily doped region over said first surface region of said semiconductor substrate and leaving exposed said second surface region of said semiconductor substrate; a semiconductor layer, including a first part formed on said first insulating film over said first surface region, and a second part formed on said semiconductor substrate in said second surface region, said second part including a single-crystalline region where said second part of said semiconductor layer contacts said semiconductor substrate in said second surface region; a capacitor comprising (a) at least a part of said first insulating film over said first surface region of said semiconductor substrate, (b) at least a part of said heavily doped region in said first surface region of said semiconductor substrate, and (c) said first part of said semiconductor layer which is disposed on said first insulating film over said first surface region of said substrate, said first part of said semiconductor layer over said first surface region comprising an information storage region; and said second part of said semiconductor layer comprising the source, channel and drain regions of a transistor, said source region being short-circuited with said first part of the semiconductor layer comprised in said capacitor.
Claim 3
Dependent Claim
33 words
A semiconductor memory device according to claim 1, wherein a second insulating film thickner than said first insulating film is formed on the semiconductor substrate surface between said first and second surface regions.
Claim 4
Dependent Claim
24 words
A semiconductor memory device according to claim 2, wherein a channel stopper having said first conductivity type is formed beneath said second insulating film.
Claim 5
Dependent Claim
49 words
A semiconductor memory device according to claim 2, wherein said first part of the semiconductor layer is polycrystalline, said channel region is formed in the single crystalline region of said second part of the semiconductor layer contacting said semiconductor substrate, and said channel region has said first conductivity type.
Claim 6
Dependent Claim
34 words
A semiconductor memory device according to claim 4, wherein said second part of the semiconductor layer includes two polycrystalline regions formed on said second insulating film for respectively contacting said source and drain regions.
Claim 7
Dependent Claim
39 words
A semiconductor memory device according to claim 5, wherein the PN junctions between said channel region and each of said source and drain regions are located in said single crystalline region of said second part of the semiconductor layer.
Claim 8
Dependent Claim
27 words
The device of claim 1, 2, 3, 4, 5 or 6, said heavily doped region having an impurity concentration of at least 5×10 18 /cm 3 .
Claim 9
Dependent Claim
15 words
The device of claim 7, said heavily doped region being not deeper than 2000 Å.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-13 | 1987-08-15 | 1988-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-13 | 1991-08-15 | 1992-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-13 | 1995-08-15 | 1996-02-14 | $7700.00 | Window Closed / Lapsed |