Semiconductor device and process for producing the same

Claim 2

A semiconductor device comprising: a semiconductor substrate having a first conductivity type; a first insulating layer on said semiconductor substrate, said first insulating layer having a window on a first part of said substrate; an integral semiconductor layer selectively covering said first part of said substrate and said first insulating layer, a first portion of said semiconductor layer being in contact with said substrate and having a first width along a first direction, at least a second portion of said semiconductor layer within said first portion being single crystalline; a thin insulating layer selectively covering said second portion of said semiconductor layer above said first part of said substrate, said thin insulating layer having a thin thickness suited for establishing a channel region thereunder in said second portion of said semiconductor layer and having a first width in said first direction that is smaller than said first width of said semiconductor layer; a gate electrode on said thin insulating layer; and an insulating component located at each of two respective ends of said semiconductor layer, said two ends comprising the two sides of said semiconductor layer that are crossed by a line parallel to said first direction, said two insulating components extending perpendicularly to said first direction along the two respective sides of said channel region and being essentially thicker than said thin insulating layer.

Claim 3

A semiconductor device comprising: a semiconductor substrate having a first conductivity type; a first insulating layer on said semiconductor substrate, said first insulating layer having a window on a first part of said substrate; an integral semiconductor layer selectively covering said first part of said substrate and said first insulating layer, a first portion of said semiconductor layer being in contact with said substrate and having a first width along a first direction, at least a second portion of said semiconductor layer within said first portion being single crystalline; a thin insulating layer selectively covering said second portion of said semiconductor layer above said first part of said substrate, said thin insulating layer having a thin thickness suited for establishing a channel region thereunder in said second portion of said semiconductor layer and having a first width in said first direction that is smaller than said first width of said semiconductor layer; a gate electrode on said thin insulating layer; an insulating component located at each of the two respective ends of said semiconductor layer, said two ends comprising the two sides of said semiconductor layer that are crossed by a line parallel to said first direction, said two insulating components extending perpendicularly to said first direction along two respective sides of said channel region and having essentially the same thickness as said thin insulating layer; and a channel doped region having said first conductivity under each of said two insulating components in said semiconductor layer.

Claim 4

A semiconductor device comprising: a semiconductor substrate having a first conductivity type; a first insulating layer on said semiconductor substrate, said first insulating layer having a window on a first part of said substrate; an integral semiconductor layer selectively covering said first part of said substrate and said first insulating layer, a first portion of said semiconductor layer being in contact with said substrate and having a first width along a first direction, at least a second portion of said semiconductor layer within said first portion being single crystalline; a thin insulating layer selectively covering said second portion of said semiconductor layer above said first part of said substrate, said thin insulating layer having a thin thickness suited for establishing a channel region thereunder in said second portion of said semiconductor layer and having a first width in said first direction that is smaller than said first width of said semiconductor layer; a gate electrode on said thin insulating layer; an insulating component located at each of the two respective ends of said semiconductor layer, said two ends comprising the two sides of said semiconductor layer that are crossed by a line parallel to said first direction, said two insulating components extending perpendicularly to said first direction along two respective sides of said channel region and having essentially the same thickness as said thin insulating layer; and a channel doped region having said first conductivity under each of said two insulating components in said semiconductor layer.

Claim 5

A semiconductor device according to claim 1 or 2, said substrate having resistivity in the range from 0.5 to 2 ohm cm.

Claim 6

A semiconductor device according to claim 1 or 1 said first insulating layer having a thickness in the range from 0.5 to 2 microns.

Claim 7

A semiconductor device according to claim 1 or 1, said semiconductor layer having a thickness of from 0.5 to 1.5 microns and said single-crystal second portion of said semiconductor layer having a body resistivity of from 0.5 to 60 ohm cm.

Claim 8

A process for producing a semiconductor device comprising the steps of: forming a first insulating layer on a semiconductor substrate of a first conductivity type, said insulating layer having a window to selectively expose a first part of said substrate, the top surface of said insulating layer being not at an essentially lower level than, the surface of said first part of said substrate; selectively forming a semiconductor layer on said first part of said substrate and on said first insulating layer, said semiconductor layer over said first part of said substrate comprising a single crystal part; forming a second insulating layer selectively on said semiconductor layer to expose a first two portions of said semiconductor layer, said first two portions being separated from one another along a first direction, and a second two portions which are separated from one another in a direction perpendicular to said first direction and which selectively overlap said window at the sides of said window oriented parallel to said first direction; changing said first and second two portions of said semiconductor layer to an insulating material; selectively forming a gate insulating layer on said semiconductor layer over said first part of said substrate, said gate insulating film being thinner than the thickness of said insulating material; forming a gate electrode on said gate insulating layer; exposing a third two portions of said semiconductor layer between said gate electrode and said first two portions; and selectively incorporating an impurity of conductivity type opposite to said first conductivity type into said third two regions of said semiconductor layer by using said gate electrode and gate insulating layer as a mask to provide said third two regions with a conductivity suitable for source and drain regions.

Claim 9

A process for producing a semiconductor device comprising the steps of: forming a first insulating layer on a semiconductor substrate of a first conductivity type, said insulating layer having a window to selectively expose a first part of said substrate, the top surface of said insulating layer being not at an essentially lower level than, the surface of said first part of said substrate; selectively forming a semiconductor layer on said first part of said substrate and on said first insulating layer, said semiconductor layer over said first part of said substrate comprising a single crystal part; forming a second insulating layer selectively on said semiconductor layer to expose a first two portions of said semiconductor layer, said first two portions being separated from one another along a first direction, and a second two portions which are separated from one another in a direction perpendicular to said first direction and which selectively overlap said window at the sides of said window oriented parallel to said first direction; changing said first and second two portions of said semiconductor layer to an insulating material; selectively forming a gate insulating layer on said semiconductor layer over said first part of said substrate, said gate insulating film being thinner than the thickness of said insulating material; forming a gate electrode on said gate insulating layer; exposing a third two portions of said semiconductor layer between said gate electrode and said first two portions; and selectively incorporating an impurity of conductivity type opposite to said first conductivity type into said third two regions of said semiconductor layer by using said gate electrode and gate insulating layer as a mask to provide said third two regions with a conductivity suitable for source and drain regions.

Claim 10

A process according to claim 6 comprising forming the surface of said substrate to have higher and lower portions, masking said higher portion of said surface of said substrate and selectively oxidizing said lower portion, and forming said window by removing said mask from said higher portion, thereby providing the top surface of said first insulating layer with essentially the same level as that of said oxidized lower portion of said substrate.

Claim 11

A process for producing a semiconductor device according to claim 6 or 7, wherein said substrate has a resistivity of from 0.5 to 2 ohm cm.

Claim 12

A process for producing the semiconductor device according to claims 6 and 7, wherein said first insulating layer has a thickness of from 0.5 to 2 microns.

Claim 13

A process for producing a semiconductor device according to claims 6 and 7, comprising forming said semiconductor layer to have a thickness of from 0.5 to 1.5 microns, and forming said single-crystal part to have a body resistivity of from 0.5 to 50 ohm cm.

Claim 14

A process for producing the semiconductor device according to claims 6 and 7, said semiconductor layer covering said first insulating layer being polycrystalline with a resistivity of from 18 to 20 ohm cm.

Claim 15

A process for producing a semiconductor device comprising the steps of: forming a first insulating layer on a substrate having a first conductivity type, said insulating layer having a window to selectively expose a first portion of said substrate, the top surface of said insulating layer being not at an essentially lower level than said first portion of said substrate; integrally forming a semiconductor layer on said first portion of said substrate and said first insulating layer, said semiconductor layer comprising a single-crystal part on said first portion and a polycrystalline part on said first insulating layer; forming a second insulating layer for selectively masking said semiconductor layer, said masking exposing a first two regions of said semiconductor layer separated from one another along a first direction and a second two regions separated from one another in a direction perpendicular to said first direction, said second two regions selectively overlapping said window; removing said semiconductor layer where not masked by said second insulating layer; forming channel stop regions on third two regions of said semiconductor layer over said first portion of substrate, said third regions being separated from one another in said perpendicular direction; forming a thin insulating layer on said semiconductor layer over said first portion of said substrate, said thin insulating layer having a thickness suitable for establishing a channel region thereunder; forming a gate electrode on said thin insulating layer; selectively exposing a fourth two regions of said semiconductor layer by using said gate electrode and said thin insulating layer as a mask, said fourth regions being separated from one another in said first direction; and selectively incorporating an impurity of conductivity type opposite to said first conductivity type into said exposed third two regions, thereby providing said third two regions with a conductivity suitable for respective source and drain regions of said semiconductor device.

Claim 16

A process for producing a semiconductor device comprising the steps of: forming a first insulating layer on a substrate having a first conductivity type, said insulating layer having a window to selectively expose a first portion of said substrate, the top surface of said insulating layer being not at an essentially lower level than said first portion of said substrate; integrally forming a semiconductor layer on said first portion of said substrate and said first insulating layer, said semiconductor layer comprising a single-crystal part on said first portion and a polycrystalline part on said first insulating layer; forming a second insulating layer for selectively masking said semiconductor layer, said masking exposing a first two regions of said semiconductor layer separated from one another along a first direction and a second two regions separated from one another in a direction perpendicular to said first direction, said second two regions selectively overlapping said window; removing said semiconductor layer where not masked by said second insulating layer; forming channel stop regions on third two regions of said semiconductor layer over said first portion of substrate, said third regions being separated from one another in said perpendicular direction; forming a thin insulating layer on said semiconductor layer over said first portion of said substrate, said thin insulating layer having a thickness suitable for establishing a channel region thereunder; forming a gate electrode on said thin insulating layer; selectively exposing a fourth two regions of said semiconductor layer by using said gate electrode and said thin insulating layer as a mask, said fourth regions being separated from one another in said first direction; and selectively incorporating an impurity of conductivity type opposite to said first conductivity type into said exposed third two regions, thereby providing said third two regions with a conductivity suitable for respective source and drain regions of said semiconductor device.

Claim 17

A process according to claim 12 comprising forming the surface of said substrate to have higher and lower portions, masking said higher portion of said substrate and selectively oxidizing said lower portion thereof, and forming said window by removing said mask from said higher portion, to provide said top surface of said first insulating layer with essentially the same level as that of said oxidized lower portion of said substrate.

Claim 18

A process for producing a semiconductor device according to claim 12 or 13 comprising forming said substrate to have a resistivity of from 0.5 to 2 ohm cm.

Claim 19

A process for producing a semiconductor device according to claim 12 or 13 comprising forming said first insulating layer to have a thickness of from 0.5 to 2 microns.

Claim 20

A process for producing a semiconductor device according to claim 12 or 13 comprising forming said semiconductor layer to have a thickness of from 0.5 to 1.5 microns, and forming said single-crystal part to have a body resistivity of from 0.5 to 50 ohm cm.

Claim 21

A process for producing the semiconductor device according to claims 12 and 13 comprising forming said polycrystalline part of said semiconductor layer to have a resistivity of from 18 to 20 ohm cm.