Patent US2362075A successfully refreshed from Google Patents.
US4413401A
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Method for making a semiconductor capacitor
Assignee: National Semiconductor Corp
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Filing: 1981-07-06
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Granted: 1983-11-08
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Expires: 2001-07-06
Abstract
Abstract This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity. Thus, the boron implanted region performs the important function of preventing a surface N type inversion layer from being formed across the semiconductor surface beneath the silicon dioxide insulating layer which could occur across the substrate P- surface if the arsenic implant region was made into the P- substrate without the P type boron implant. The arsenic implant is of N type conductivity and has a higher concentration of impurities than the boron implant region. The dielectric portion of the semiconductor capacitor is the portion of the silicon dioxide layer located on the surface of the arsenic implanted region. A doped polysilicon electrode is formed over this portion of the silicon dioxide insulating layer and provides the other plate of the capacitor structure. In another embodiment that is disclosed, this above described semiconductor capacitor structure or device is combined with an MOS device in a single integrated semiconductor structure in order to provide a single MOS memory cell for dynamic random access memory chip utilizing the MOS device and the capacitor. Preferably, the semiconductor capacitor is shown as a connected extension of either the source or drain region of the MOS device.
Inventors
- 👤 Thomas Klein
- 👤 Andrew G. Varadi
- 👤 Charles E. Boettcher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 01:33
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
203 words
A method for making a semiconductor capacitor device comprising the steps of: forming a semiconductor region of one conductivity type within a higher resistivity semiconductor region of the same type conductivity; forming a shallow semiconductor region of opposite conductivity type within said semiconductor region of one conductivity type located within said higher resistivity semiconductor region of the same one type conductivity; forming an insulating layer on a surface of said semiconductor region of one conductivity type, said higher resistivity semiconductor region of the same one type conductivity and said shallow semiconductor region of opposite conductivity type; forming an electrically conductive electrode on a surface portion of said insulating layer located over said shallow semiconductor region of opposite conductivity type, said electrode being contoured to have an area that covers a major portion of the area of said shallow semiconductor region of opposite conductivity type; and depositing an electrical contact to make an electrical connection to said shallow semiconductor region of opposite conductivity type, said electrically conductive electrode being one plate of the semiconductor capacitor device, said insulating layer being the dielectric of the semiconductor capacitor device, and said semiconductor region of opposite conductivity type being the other plate of the semiconductor capacitor device.
Claim 2
Independent Claim
203 words
A method for making a semiconductor capacitor device comprising the steps of: forming a semiconductor region of one conductivity type within a higher resistivity semiconductor region of the same type conductivity; forming a shallow semiconductor region of opposite conductivity type within said semiconductor region of one conductivity type located within said higher resistivity semiconductor region of the same one type conductivity; forming an insulating layer on a surface of said semiconductor region of one conductivity type, said higher resistivity semiconductor region of the same one type conductivity and said shallow semiconductor region of opposite conductivity type; forming an electrically conductive electrode on a surface portion of said insulating layer located over said shallow semiconductor region of opposite conductivity type, said electrode being contoured to have an area that covers a major portion of the area of said shallow semiconductor region of opposite conductivity type; and depositing an electrical contact to make an electrical connection to said shallow semiconductor region of opposite conductivity type, said electrically conductive electrode being one plate of the semiconductor capacitor device, said insulating layer being the dielectric of the semiconductor capacitor device, and said semiconductor region of opposite conductivity type being the other plate of the semiconductor capacitor device.
Claim 3
Dependent Claim
50 words
A method in accordance with claim 1 wherein said step of forming said semiconductor region of one conductivity type within a higher resistivity semiconductor region of the same type conductivity comprising ion implanting impurities of said one conductivity type into said higher resistivity semiconductor region of said one conductivity type.
Claim 4
Dependent Claim
49 words
A method in accordance with claim 1 wherein said step of forming said shallow semiconductor region of opposite conductivity type comprising ion implanting impurities of said opposite conductivity type into said semiconductor region of one conductivity type located within said higher resistivity semiconductor region of said one conductivity type.
Claim 5
Dependent Claim
49 words
A method in accordance with claim 2 wherein said step of forming said shallow semiconductor region of opposite conductivity type comprising ion implanting impurities of said opposite conductivity type into said semiconductor region of one conductivity type located within said higher resistivity semiconductor region of said one conductivity type.
Claim 6
Dependent Claim
15 words
A method in accordance with claim 2 wherein said ion implanted impurities being boron ions.
Claim 7
Dependent Claim
15 words
A method in accordance with claim 3 wherein said ion implanted impurities being arsenic ions.
Claim 8
Dependent Claim
39 words
A method in accordance with claim 4 wherein said ion implanted impurities forming said semiconductor region of one conductivity type being boron ions, said ion implanted impurities forming said shallow semiconductor region of opposite conductivity type being arsenic ions.
Claim 9
Dependent Claim
22 words
A method in accordance with claim 1 wherein said step of forming said insulating layer comprising thermally growing a silicon dioxide layer.
Claim 10
Dependent Claim
67 words
A method in accordance with claim 1 wherein said step of forming said electrically conductive electrode comprising depositing a polysilicon layer on said insulating layer, doping said deposited polysilicon layer to make it electrically conductive, and removing portions of said doped polysilicon layer to form said electrically conductive electrode on the surface portion of said insulating layer located over said shallow semiconductor region of opposite conductivity type.
Claim 11
Dependent Claim
52 words
A method in accordance with claim 1 wherein said step of depositing an electrical contact to make an electrical connection to said shallow semiconductor region of opposite conductivity type comprising evaporating a metal contact through an opening in said insulating layer to electrically contact said shallow semiconductor region of opposite conductivity type.
Claim 12
Dependent Claim
181 words
A method in accordance with claim 1 wherein said step of forming said semiconductor region of one conductivity type within a higher resistivity semiconductor region of the same type conductivity comprising ion implanting impurities of said one conductivity type into said higher resistivity semiconductor region of said one conductivity type, said step of forming said shallow semiconductor region of opposite conductivity type comprising ion implanting impurities of said opposite conductivity type into said semiconductor region of one conductivity type located within said higher resistivity semiconductor region of said one conductivity type, said ion implanted impurities forming said shallow semiconductor region of opposite conductivity type being arsenic ions, said step of forming said insulating layer comprising thermally growing a silicon dioxide layer, and said step of forming said electrically conductive electrode comprising depositing a polysilicon layer on said insulating layer, doping said deposited polysilicon layer to make it electrically conductive, and removing portions of said doped polysilicon layer to form said electrically conductive electrode on the surface portion of said insulating layer located over said shallow semiconductor region of opposite conductivity type.
Claim 13
Independent Claim
206 words
A method for making a semiconductor capacitor device comprising the steps of: forming a semiconductor region of one conductivity type within a higher resistivity semiconductor region of the same type conductivity; forming a shallow semiconductor region of opposite conductivity type having at least one portion located within said semiconductor region of one conductivity type located within said higher resistivity semiconductor region of the same one type conductivity; forming an insulating layer on a surface of said semiconductor region of one conductivity type, said higher resistivity semiconductor region of the same one type conductivity, and said shallow semiconductor region of opposite conductivity type; forming an electrically conductive electrode on at least one surface portion of said insulating layer located over said shallow semiconductor region of opposite conductivity type; said electrode being contoured to have an area that covers a major portion of the area of said shallow semiconductor region of opposite conductivity type, and providing an electrical connection to said shallow semiconductor region of opposite conductivity type, said electrically conductive electrode being one plate of the semiconductor capacitor device, said insulating layer being the dielectric of the semiconductor capacitor device, and said semiconductor region of opposite conductivity type being the other plate of the semiconductor capacitor device.
Claim 14
Independent Claim
206 words
A method for making a semiconductor capacitor device comprising the steps of: forming a semiconductor region of one conductivity type within a higher resistivity semiconductor region of the same type conductivity; forming a shallow semiconductor region of opposite conductivity type having at least one portion located within said semiconductor region of one conductivity type located within said higher resistivity semiconductor region of the same one type conductivity; forming an insulating layer on a surface of said semiconductor region of one conductivity type, said higher resistivity semiconductor region of the same one type conductivity, and said shallow semiconductor region of opposite conductivity type; forming an electrically conductive electrode on at least one surface portion of said insulating layer located over said shallow semiconductor region of opposite conductivity type; said electrode being contoured to have an area that covers a major portion of the area of said shallow semiconductor region of opposite conductivity type, and providing an electrical connection to said shallow semiconductor region of opposite conductivity type, said electrically conductive electrode being one plate of the semiconductor capacitor device, said insulating layer being the dielectric of the semiconductor capacitor device, and said semiconductor region of opposite conductivity type being the other plate of the semiconductor capacitor device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-11-07 | 1987-05-09 | 1987-11-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-11-07 | 1991-05-09 | 1991-11-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-11-07 | 1995-05-09 | 1995-11-08 | $7700.00 | Window Closed / Lapsed |