US5563104A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Reduction of pattern sensitivity in ozone-teos deposition via a two-step (low and high temperature) process
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-06-23
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Granted: 1996-10-08
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Expires: 2015-06-23
Abstract
Abstract An improved method of ozone-TEOS deposition with reduced pattern sensitivity using a two-step low and high temperature process is described. Semiconductor device structures are provided in and on a semiconductor substrate. A conducting layer is deposited overlying the surfaces of the semiconductor device structures and patterned to form conducting lines. An underlayer is deposited overlying the patterned conducting layer. A dielectric layer is deposited in two steps. A first ozone-TEOS layer is deposited over the surfaces of the conducting layer at a first temperature to a first thickness. A second ozone-TEOS layer is deposited over the first ozone-TEOS layer at a second temperature and to a second thickness wherein the second temperature is higher than the first temperature and the second thickness is greater than the first thickness completing the dielectric layer.
Inventors
- 👤 Syun-Ming Jang
- 👤 Lu-Min Liu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:31
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/66; H10P14/662; H10P14/65; H10P14/6502; H10P14/6506; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
144 words
A method of manufacturing an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer to form conducting lines; depositing a dielectric layer comprising: conformally depositing a first oxide layer over the surfaces of said conducting layer wherein said first oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS and is deposited at a first temperature of between about 350° to 370° C. and to a first thickness; and depositing a second oxide layer over said first oxide layer wherein said second oxide layer is deposited at a second temperature of between about 430° to 450° C. and to a second thickness wherein said second thickness is greater than said first thickness to complete said dielectric layer; and completing the fabrication of said integrated circuit.
Claim 2
Independent Claim
144 words
A method of manufacturing an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer to form conducting lines; depositing a dielectric layer comprising: conformally depositing a first oxide layer over the surfaces of said conducting layer wherein said first oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS and is deposited at a first temperature of between about 350° to 370° C. and to a first thickness; and depositing a second oxide layer over said first oxide layer wherein said second oxide layer is deposited at a second temperature of between about 430° to 450° C. and to a second thickness wherein said second thickness is greater than said first thickness to complete said dielectric layer; and completing the fabrication of said integrated circuit.
Claim 3
Dependent Claim
29 words
A method according to claim 1 wherein said depositing said dielectric layer further comprises depositing a nucleation layer underlying said first oxide layer and overlying said patterned conducting layer.
Claim 4
Dependent Claim
18 words
A method according to claim 2 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited silicon oxide.
Claim 5
Dependent Claim
18 words
A method according to claim 2 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited TEOS oxide.
Claim 6
Dependent Claim
17 words
A method according to claim 1 wherein said first thickness is between about 500 to 2000 Angstroms.
Claim 7
Dependent Claim
17 words
A method according to claim 1 wherein said second oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS.
Claim 8
Dependent Claim
17 words
A method according to claim 1 wherein said second thickness is between about 3000 to 4500 Angstroms.
Claim 9
Dependent Claim
21 words
A method according to claim 1 wherein the sum of said first and second thicknesses is more than about 4000 Angstroms.
Claim 10
Dependent Claim
24 words
A method according to claim 1 wherein said first oxide deposited at said first temperature reduces the pattern sensitivity of said second oxide deposition.
Claim 11
Dependent Claim
22 words
A method according to claim 1 wherein said second oxide deposited at said second temperature increases the quality of said dielectric layer.
Claim 12
Independent Claim
148 words
A method of manufacturing an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer to form conducting lines; depositing a dielectric layer comprising: depositing a nucleation layer over the surfaces of said conducting layer; depositing a first oxide layer overlying said nucleation layer wherein said first oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS and is deposited at a first temperature of between about 350°-370° C. to a first thickness; and depositing a second oxide layer over said first oxide layer wherein said second oxide layer is deposited at a second temperature of between about 430° to 450° C. and to a second thickness wherein said second thickness is greater than said first thickness to complete said dielectric layer; and completing the fabrication of said integrated circuit.
Claim 13
Independent Claim
148 words
A method of manufacturing an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer to form conducting lines; depositing a dielectric layer comprising: depositing a nucleation layer over the surfaces of said conducting layer; depositing a first oxide layer overlying said nucleation layer wherein said first oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS and is deposited at a first temperature of between about 350°-370° C. to a first thickness; and depositing a second oxide layer over said first oxide layer wherein said second oxide layer is deposited at a second temperature of between about 430° to 450° C. and to a second thickness wherein said second thickness is greater than said first thickness to complete said dielectric layer; and completing the fabrication of said integrated circuit.
Claim 14
Dependent Claim
18 words
A method according to claim 11 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited silicon oxide.
Claim 15
Dependent Claim
18 words
A method according to claim 11 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited TEOS oxide.
Claim 16
Dependent Claim
17 words
A method according to claim 11 wherein said first thickness is between about 500 to 2000 Angstroms.
Claim 17
Dependent Claim
17 words
A method according to claim 11 wherein said second oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS.
Claim 18
Dependent Claim
17 words
A method according to claim 11 wherein said second thickness is between about 3000 to 4500 Angstroms.
Claim 19
Dependent Claim
21 words
A method according to claim 11 wherein the sum of said first and second thicknesses is more than about 4000 Angstroms.
Claim 20
Dependent Claim
24 words
A method according to claim 11 wherein said first oxide deposited at said first temperature reduces the pattern sensitivity of said second oxide deposition.
Claim 21
Dependent Claim
22 words
A method according to claim 11 wherein said second oxide deposited at said second temperature increases the quality of said dielectric layer.
Claim 22
Independent Claim
175 words
A method of manufacturing an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer to form conducting lines; depositing a dielectric layer comprising: depositing a nucleation layer over the surfaces of said conducting layer; depositing a first oxide layer overlying said nucleation layer wherein said first oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS and is deposited at a temperature of between about 350° to 370° C. to a first thickness; and depositing a second oxide layer over said first oxide layer wherein said second oxide layer is deposited at a temperature of between about 430° to 450° C. wherein the presence of said first oxide layer reduces the pattern sensitivity of said second oxide deposition and wherein said second oxide layer is deposited to a second thickness wherein said second thickness is greater than said first thickness to increase the quality of said dielectric layer; and completing the fabrication of said integrated circuit.
Claim 23
Independent Claim
175 words
A method of manufacturing an integrated circuit comprising: providing semiconductor device structures in and on a semiconductor substrate; depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer to form conducting lines; depositing a dielectric layer comprising: depositing a nucleation layer over the surfaces of said conducting layer; depositing a first oxide layer overlying said nucleation layer wherein said first oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS and is deposited at a temperature of between about 350° to 370° C. to a first thickness; and depositing a second oxide layer over said first oxide layer wherein said second oxide layer is deposited at a temperature of between about 430° to 450° C. wherein the presence of said first oxide layer reduces the pattern sensitivity of said second oxide deposition and wherein said second oxide layer is deposited to a second thickness wherein said second thickness is greater than said first thickness to increase the quality of said dielectric layer; and completing the fabrication of said integrated circuit.
Claim 24
Dependent Claim
18 words
A method according to claim 20 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited silicon oxide.
Claim 25
Dependent Claim
18 words
A method according to claim 20 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited TEOS oxide.
Claim 26
Dependent Claim
17 words
A method according to claim 20 wherein said first thickness is between about 500 to 2000 Angstroms.
Claim 27
Dependent Claim
17 words
A method according to claim 20 wherein said second oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS.
Claim 28
Dependent Claim
17 words
A method according to claim 20 wherein said second thickness is between about 3000 to 4500 Angstroms.
Claim 29
Dependent Claim
21 words
A method according to claim 20 wherein the sum of said first and second thicknesses is more than about 4000 Angstroms.
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