US5460993A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-04-03
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Granted: 1995-10-24
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Expires: 2015-04-03
Abstract
Abstract A method of forming different width spacers for NMOS and PMOS in the fabrication of an integrated circuit is described. A semiconductor substrate is provided wherein NMOS and PMOS regions are separated by an isolation region. Gate electrodes are formed in the NMOS and PMOS regions. Lightly doped regions are implanted into the semiconductor substrate within the NMOS and PMOS regions. A spacer material layer is deposited over the gate electrodes in the NMOS and PMOS regions and etched away to leave spacers on the sidewalls of the gate electrodes. The NMOS region is covered with a photoresist mask. Heavily doped source and drain regions are implanted into the semiconductor substrate within the PMOS region. The photoresist mask is removed. After the PMOS implantation, a portion of the spacers is etched away to leave narrower spacers on the sidewalls of the gate electrodes. The PMOS region is covered with a photoresist mask. Heavily doped source and drain regions are implanted into the semiconductor substrate within the NMOS region. The photoresist mask is removed and the fabrication of the integrated circuit is completed.
Inventors
- 👤 Shun-Liang Hsu
- 👤 Shyh-Chyi Wong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:43
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0184; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/8316; H10D84/85; H10D84/856; H10D84/8311
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
176 words
A method of forming different width spacers for NMOS and PMOS in the fabrication of an integrated circuit comprising: providing a semiconductor substrate wherein NMOS and PMOS regions are separated by an isolation region; forming gate electrodes in said NMOS and PMOS regions; implanting lightly doped regions into said semiconductor substrate within said NMOS and PMOS regions; depositing a spacer material layer over said gate electrodes in said NMOS and PMOS regions and etching away said spacer material layer to leave spacers on the sidewalls of said gate electrodes; covering said NMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said PMOS region; removing said photoresist mask; after said implanting within said PMOS region, etching away a portion of said spacers to leave narrower spacers on the sidewalls of said gate electrodes; covering said PMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said NMOS region; removing said photoresist mask; and completing the fabrication of said integrated circuit.
Claim 2
Independent Claim
176 words
A method of forming different width spacers for NMOS and PMOS in the fabrication of an integrated circuit comprising: providing a semiconductor substrate wherein NMOS and PMOS regions are separated by an isolation region; forming gate electrodes in said NMOS and PMOS regions; implanting lightly doped regions into said semiconductor substrate within said NMOS and PMOS regions; depositing a spacer material layer over said gate electrodes in said NMOS and PMOS regions and etching away said spacer material layer to leave spacers on the sidewalls of said gate electrodes; covering said NMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said PMOS region; removing said photoresist mask; after said implanting within said PMOS region, etching away a portion of said spacers to leave narrower spacers on the sidewalls of said gate electrodes; covering said PMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said NMOS region; removing said photoresist mask; and completing the fabrication of said integrated circuit.
Claim 3
Dependent Claim
14 words
A method according to claim 1 wherein said gate electrodes are composed of polysilicon.
Claim 4
Dependent Claim
46 words
A method according to claim 1 wherein said lightly doped regions within said NMOS regions are formed by implanting phosphorus ions with a dosage of between about 8 E 12 to 6 E 13 atoms/cm 2 at an energy of between about 25 to 40 KeV.
Claim 5
Dependent Claim
46 words
A method according to claim 1 wherein said lightly doped regions within said NMOS regions are formed by implanting arsenic ions with a dosage of between about 8 E 12 to 6 E 13 atoms/cm 2 at an energy of between about 5 to 40 KeV.
Claim 6
Dependent Claim
47 words
A method according to claim 1 wherein said lightly doped regions within said PMOS regions are formed by implanting BF 2 ions with a dosage of between about 8 E 12 to 6 E 13 atoms/cm 2 at an energy of between about 20 to 40 KeV.
Claim 7
Dependent Claim
28 words
A method according to claim 1 wherein said spacer material layer comprises polysilicon and is deposited by LPCVD to a thickness of between about 1500 to 3000 Angstroms.
Claim 8
Dependent Claim
29 words
A method according to claim 1 wherein said spacer material layer comprises an oxide and is deposited by LPCVD to a thickness of between about 1500 to 3000 Angstroms.
Claim 9
Dependent Claim
23 words
A method according to claim 1 wherein said spacers before said PMOS implantation have a width of between about 1300 to 2500 Angstroms.
Claim 10
Dependent Claim
47 words
A method according to claim 1 wherein said heavily doped regions within said PMOS regions are formed by implanting BF 2 ions with a dosage of between about 1 E 15 to 3 E 15 atoms/cm 2 at an energy of between about 50 to 70 KeV.
Claim 11
Dependent Claim
20 words
A method according to claim 1 wherein said narrower spacers have a width of between about 1000 to 1700 Angstroms.
Claim 12
Dependent Claim
46 words
A method according to claim 1 wherein said heavily doped regions within said NMOS regions are formed by implanting arsenic ions with a dosage of between about 2 E 15 to 5 E 15 atoms/cm 2 at an energy of between about 50 to 70 KeV.
Claim 13
Independent Claim
204 words
A method of forming different width spacers for NMOS and PMOS in the fabrication of an integrated circuit comprising: providing a semiconductor substrate wherein NMOS and PMOS regions are separated by an isolation region; providing a gate oxide layer over the surface of said semiconductor substrate; depositing a layer of polysilicon overlying said gate oxide layer and patterning said polysilicon layer to form gate electrodes in said NMOS and PMOS regions; implanting lightly doped regions into said semiconductor substrate within said NMOS and PMOS regions; depositing a spacer material layer over said gate electrodes in said NMOS and PMOS regions and etching away said spacer material layer to leave spacers on the sidewalls of said gate electrodes; covering said NMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said PMOS region; removing said photoresist mask; after said implanting within said PMOS region, etching away a portion of said spacers to leave narrower spacers on the sidewalls of said gate electrodes; covering said PMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said NMOS region; removing said photoresist mask; and completing the fabrication of said integrated circuit.
Claim 14
Independent Claim
204 words
A method of forming different width spacers for NMOS and PMOS in the fabrication of an integrated circuit comprising: providing a semiconductor substrate wherein NMOS and PMOS regions are separated by an isolation region; providing a gate oxide layer over the surface of said semiconductor substrate; depositing a layer of polysilicon overlying said gate oxide layer and patterning said polysilicon layer to form gate electrodes in said NMOS and PMOS regions; implanting lightly doped regions into said semiconductor substrate within said NMOS and PMOS regions; depositing a spacer material layer over said gate electrodes in said NMOS and PMOS regions and etching away said spacer material layer to leave spacers on the sidewalls of said gate electrodes; covering said NMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said PMOS region; removing said photoresist mask; after said implanting within said PMOS region, etching away a portion of said spacers to leave narrower spacers on the sidewalls of said gate electrodes; covering said PMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said NMOS region; removing said photoresist mask; and completing the fabrication of said integrated circuit.
Claim 15
Dependent Claim
46 words
A method according to claim 12 wherein said lightly doped regions within said NMOS regions are formed by implanting phosphorus ions with a dosage of between about 8 E 12 to 6 E 13 atoms/cm 2 at an energy of between about 25 to 40 KeV.
Claim 16
Dependent Claim
46 words
A method according to claim 12 wherein said lightly doped regions within said NMOS regions are formed by implanting arsenic ions with a dosage of between about 8 E 12 to 6 E 13 atoms/cm 2 at an energy of between about 25 to 40 KeV.
Claim 17
Dependent Claim
47 words
A method according to claim 12 wherein said lightly doped regions within said PMOS regions are formed by implanting BF 2 ions with a dosage of between about 8 E 12 to 6 E 13 atoms/cm 2 at an energy of between about 20 to 40 KeV.
Claim 18
Dependent Claim
28 words
A method according to claim 12 wherein said spacer material layer comprises polysilicon and is deposited by LPCVD to a thickness of between about 1500 to 3000 Angstroms.
Claim 19
Dependent Claim
29 words
A method according to claim 12 wherein said spacer material layer comprises an oxide and is deposited by LPCVD to a thickness of between about 1500 to 3000 Angstroms.
Claim 20
Dependent Claim
23 words
A method according to claim 12 wherein said spacers before said PMOS implantation have a width of between about 1300 to 2500 Angstroms.
Claim 21
Dependent Claim
47 words
A method according to claim 12 wherein said heavily doped regions within said PMOS regions are formed by implanting BF 2 ions with a dosage of between about 1 E 15 to 3 E 15 atoms/cm 2 at an energy of between about 50 to 70 KeV.
Claim 22
Dependent Claim
20 words
A method according to claim 12 wherein said narrower spacers have a width of between about 1000 to 1700 Angstroms.
Claim 23
Dependent Claim
46 words
A method according to claim 12 wherein said heavily doped regions within said NMOS regions are formed by implanting arsenic ions with a dosage of between about 2 E 15 to 5 E 15 atoms/cm 2 at an energy of between about 50 to 70 KeV.
Claim 24
Independent Claim
203 words
A method of forming different width spacers for NMOS and PMOS in the fabrication of an integrated circuit comprising: providing a semiconductor substrate wherein NMOS and PMOS regions are separated by an isolation region; forming gate electrodes in said NMOS and PMOS regions; implanting lightly doped regions into said semiconductor substrate within said NMOS and PMOS regions; depositing a spacer material layer over said gate electrodes in said NMOS and PMOS regions and etching away said spacer material layer to leave spacers on the sidewalls of said gate electrodes wherein said spacers have a width of between about 1500 to 3000 Angstroms; covering said NMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said PMOS region; removing said photoresist mask; after said implanting within said PMOS region, etching away a portion of said spacers to leave narrower spacers on the sidewalls of said gate electrodes wherein said narrower spacers have a width of between about 1000 to 1700 Angstroms; covering said PMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said NMOS region; removing said photoresist mask; and completing the fabrication of said integrated circuit.
Claim 25
Independent Claim
203 words
A method of forming different width spacers for NMOS and PMOS in the fabrication of an integrated circuit comprising: providing a semiconductor substrate wherein NMOS and PMOS regions are separated by an isolation region; forming gate electrodes in said NMOS and PMOS regions; implanting lightly doped regions into said semiconductor substrate within said NMOS and PMOS regions; depositing a spacer material layer over said gate electrodes in said NMOS and PMOS regions and etching away said spacer material layer to leave spacers on the sidewalls of said gate electrodes wherein said spacers have a width of between about 1500 to 3000 Angstroms; covering said NMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said PMOS region; removing said photoresist mask; after said implanting within said PMOS region, etching away a portion of said spacers to leave narrower spacers on the sidewalls of said gate electrodes wherein said narrower spacers have a width of between about 1000 to 1700 Angstroms; covering said PMOS region with a photoresist mask; implanting heavily doped source and drain regions into said semiconductor substrate within said NMOS region; removing said photoresist mask; and completing the fabrication of said integrated circuit.
Claim 26
Dependent Claim
28 words
A method according to claim 22 wherein said spacer material layer comprises polysilicon and is deposited by LPCVD to a thickness of between about 1500 to 3000 Angstroms.
Claim 27
Dependent Claim
29 words
A method according to claim 22 wherein said spacer material layer comprises an oxide and is deposited by LPCVD to a thickness of between about 1500 to 3000 Angstroms.
References Cited (Backward Citations)
DE269944C
Cited
US4642878A
Cited
EP0240781A2
Cited
US4760033A
Cited
EP0403368A1
Cited
US5296401A
Cited
US5091763A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-10-23 | 1999-04-24 | 1999-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-23 | 2003-04-24 | 2003-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-23 | 2007-04-24 | 2007-10-24 | $7700.00 | Window Closed / Lapsed |