Method of making truly complementary and self-aligned bipolar and CMOS transistor structures with minimized base and gate resistances and parasitic capacitance

Claim 1

A method for forming an integrated circuit having complementary bipolar transistors with minimized extrinsic base resistance and CMOS devices with minimized gate resistances on a silicon substrate, wherein the substrate has been selectively formed so as to be P-type in the regions where PNP bipolar and NMOS are formed and to be N-type in the regions where NPN bipolar and PMOS devices are formed and has active regions and field oxide regions defined thereon, comprising the steps of: depositing a polysilicon layer on top of the substrate; depositing a silicide layer on top of the polysilicon layer and selectively doping the silicide layer using a first photoresist mask; forming a low temperature deposited oxide layer (LTO) on top of the silicide layer; selectively etching the LTO, silicide, and polysilicon layers so as to define extrinsic base regions of the bipolar transistors and gate regions of the CMOS devices in regions where the LTO, silicide, and polysilicon layers were not etched away; oxidizing the substrate to form a thin oxide layer to cover any areas on the substrate that are no longer covered by oxide and to densify the LTO; selectively implanting a P-type impurity into NPN bases and PMOS sources and drains using the remaining LTO, silicide, and polysilicon to self-align the NPN bases and the PMOS sources and drains to those remaining LTO, silicide, and polysilicon layers and using a second photoresist mask to protect regions unintended to be implanted with P-type dopant; selectively implanting an N-type impurity into PNP bases and NMOS sources and drains using the remaining LTO, silicide, and polysilicon to self-align the PNP bases and the NMOS sources and drains to those remaining LTO, silicide, and polysilicon layers and using a third photoresist mask to protect regions unintended to be implanted with N-type dopant; depositing nitride and etching the nitride to form inside spacers on vertical surfaces of the remaining LTO, silicide, and polysilicon layers resulting from the selective etching step; etching away portions of the thin oxide layer where NPN collector and emitter areas and NMOS source and drain areas are to be formed and implanting the N-type impurity into those areas, such that the emitter areas are self-aligned by the inside spacers; and etching away portions of the thin oxide layer where PNP collector and emitter areas and PMOS source and drain areas are to be formed and implanting the P-type impurity into those areas, such that the emitter areas are self-aligned by the inside spacers.

Claim 2

A method for forming an integrated circuit having complementary bipolar transistors with minimized extrinsic base resistance and CMOS devices with minimized gate resistances on a silicon substrate, wherein the substrate has been selectively formed so as to be P-type in the regions where PNP bipolar and NMOS are formed and to be N-type in the regions where NPN bipolar and PMOS devices are formed and has active regions and field oxide regions defined thereon, comprising the steps of: depositing a polysilicon layer on top of the substrate; depositing a silicide layer on top of the polysilicon layer and selectively doping the silicide layer using a first photoresist mask; forming a low temperature deposited oxide layer (LTO) on top of the silicide layer; selectively etching the LTO, silicide, and polysilicon layers so as to define extrinsic base regions of the bipolar transistors and gate regions of the CMOS devices in regions where the LTO, silicide, and polysilicon layers were not etched away; oxidizing the substrate to form a thin oxide layer to cover any areas on the substrate that are no longer covered by oxide and to densify the LTO; selectively implanting a P-type impurity into NPN bases and PMOS sources and drains using the remaining LTO, silicide, and polysilicon to self-align the NPN bases and the PMOS sources and drains to those remaining LTO, silicide, and polysilicon layers and using a second photoresist mask to protect regions unintended to be implanted with P-type dopant; selectively implanting an N-type impurity into PNP bases and NMOS sources and drains using the remaining LTO, silicide, and polysilicon to self-align the PNP bases and the NMOS sources and drains to those remaining LTO, silicide, and polysilicon layers and using a third photoresist mask to protect regions unintended to be implanted with N-type dopant; depositing nitride and etching the nitride to form inside spacers on vertical surfaces of the remaining LTO, silicide, and polysilicon layers resulting from the selective etching step; etching away portions of the thin oxide layer where NPN collector and emitter areas and NMOS source and drain areas are to be formed and implanting the N-type impurity into those areas, such that the emitter areas are self-aligned by the inside spacers; and etching away portions of the thin oxide layer where PNP collector and emitter areas and PMOS source and drain areas are to be formed and implanting the P-type impurity into those areas, such that the emitter areas are self-aligned by the inside spacers.

Claim 10

A method for forming an integrated circuit having complementary bipolar transistors having minimized extrinsic base resistance and CMOS devices having minimized gate resistance on a silicon substrate, wherein the substrate has been selectively formed so as to be P-type in the regions where PNP bipolar and NMOS devices are formed and to be N-type in the regions where NPN bipolar and PMOS devices are formed and has active regions and field oxide regions defined thereon, comprising the steps of: depositing a silicide layer on top of the substrate and selectively doping the silicide layer using a first photoresist mask; forming an low temperature deposited oxide layer (LTO) on top of the silicide layer; selectively etching the LTO and silicide layers so as to define extrinsic base regions of the bipolar transistors and gate regions of the CMOS devices in regions-where the LTO and silicide layers were not etched away; oxidizing the substrate to form a thin oxide layer to cover any areas on the substrate that are no longer covered by oxide and to densify the LTO; selectively implanting a P-type impurity into NPN bases and PMOS sources and drains using the remaining LTO and silicide to self-align the NPN bases and the PMOS sources and drains to those remaining LTO and silicide layers and using a second photoresist mask to protect regions unintended to be implanted with P-type dopant; selectively implanting an N-type impurity into PNP bases and NMOS sources and drains using the remaining LTO and silicide to self-align the PNP bases and the NMOS sources and drains to those remaining LTO and silicide layers and using a third photoresist mask to protect regions unintended to be implanted with N-type dopant; depositing nitride and etching the nitride to form inside spacers on vertical surfaces of the remaining LTO and silicide layers resulting from the selective etching step; etching away portions of the thin oxide layer where NPN collector and emitter areas and NMOS source and drain areas are to be formed and implanting the N-type impurity into those areas, such that the emitter areas are self-aligned by the inside spacers; and etching away portions of the thin oxide layer where PNP collector and emitter areas and PMOS source and drain areas are to be formed and implanting the P-type impurity into those areas, such that the emitter areas are self-aligned by the inside spacers.

Claim 11

A method for forming an integrated circuit having complementary bipolar transistors having minimized extrinsic base resistance and CMOS devices having minimized gate resistance on a silicon substrate, wherein the substrate has been selectively formed so as to be P-type in the regions where PNP bipolar and NMOS devices are formed and to be N-type in the regions where NPN bipolar and PMOS devices are formed and has active regions and field oxide regions defined thereon, comprising the steps of: depositing a silicide layer on top of the substrate and selectively doping the silicide layer using a first photoresist mask; forming an low temperature deposited oxide layer (LTO) on top of the silicide layer; selectively etching the LTO and silicide layers so as to define extrinsic base regions of the bipolar transistors and gate regions of the CMOS devices in regions-where the LTO and silicide layers were not etched away; oxidizing the substrate to form a thin oxide layer to cover any areas on the substrate that are no longer covered by oxide and to densify the LTO; selectively implanting a P-type impurity into NPN bases and PMOS sources and drains using the remaining LTO and silicide to self-align the NPN bases and the PMOS sources and drains to those remaining LTO and silicide layers and using a second photoresist mask to protect regions unintended to be implanted with P-type dopant; selectively implanting an N-type impurity into PNP bases and NMOS sources and drains using the remaining LTO and silicide to self-align the PNP bases and the NMOS sources and drains to those remaining LTO and silicide layers and using a third photoresist mask to protect regions unintended to be implanted with N-type dopant; depositing nitride and etching the nitride to form inside spacers on vertical surfaces of the remaining LTO and silicide layers resulting from the selective etching step; etching away portions of the thin oxide layer where NPN collector and emitter areas and NMOS source and drain areas are to be formed and implanting the N-type impurity into those areas, such that the emitter areas are self-aligned by the inside spacers; and etching away portions of the thin oxide layer where PNP collector and emitter areas and PMOS source and drain areas are to be formed and implanting the P-type impurity into those areas, such that the emitter areas are self-aligned by the inside spacers.