US5164333A
Expired / Lapsed
US
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Method for manufacturing a multi-layer gate electrode for a mos transistor
Assignee: Siemens AG
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Filing: 1991-04-29
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Granted: 1992-11-17
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Expires: 2011-04-29
Abstract
Abstract A multi-layer gate electrode is provided to prevent dopant depletion of a polysilicon in the manufacture of the electrode containing doped polysilicon and metal silicide. First, a multi-layer structure is produced containing a doped polysilicon structure, a diffusion barrier structure and a silicon structure. After deposition of a metal layer covering the multi-layer structure, a metal silicide structure is produced from the silicon structure and the metal layer in a tempering process. The diffusion barrier structure thereby prevents diffusion of dopant out of the polysilicon structure into the metal silicide structure. This may be used in a salicide process.
Inventors
- 👤 Udo Schwalke
- 👤 Hellmut Joswig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:45
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/664
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
142 words
A method for producing a multi-layer gate electrode containing doped polysilicon and metal silicide in a MOS transistor, comprising the steps of: producing a multi-layer structure having side walls on a substrate provided with a gate oxide, said multi-layer structure being produced at a location prescribed for a multi-layer gate electrode, said multi-layer structure including a doped polysilicon structure on said substrate, a diffusion barrier structure on said doped polysilicon structure and a silicon structure on said diffusion barrier structure; producing spacers at said side walls of said multi-layer structure; applying a metal layer onto said substrate and said multi-layer structure; and producing a metal silicide structure from said metal layer and said silicon structure using a temperature treatment; wherein said diffusion barrier structure is of a material which prevents diffusion of dopant from said polysilicon structure into said metal silicide structure.
Claim 2
Independent Claim
142 words
A method for producing a multi-layer gate electrode containing doped polysilicon and metal silicide in a MOS transistor, comprising the steps of: producing a multi-layer structure having side walls on a substrate provided with a gate oxide, said multi-layer structure being produced at a location prescribed for a multi-layer gate electrode, said multi-layer structure including a doped polysilicon structure on said substrate, a diffusion barrier structure on said doped polysilicon structure and a silicon structure on said diffusion barrier structure; producing spacers at said side walls of said multi-layer structure; applying a metal layer onto said substrate and said multi-layer structure; and producing a metal silicide structure from said metal layer and said silicon structure using a temperature treatment; wherein said diffusion barrier structure is of a material which prevents diffusion of dopant from said polysilicon structure into said metal silicide structure.
Claim 3
Dependent Claim
33 words
A method as claimed in claim 1, wherein said metal layer is applied to simultaneously cover said multi-layer structure and prescribed locations on said substrate for a source terminal and a drain terminal.
Claim 4
Dependent Claim
47 words
A method as claimed in claim 2, further comprising the step of: producing a source region and a drain region in said substrate by ion implantation before said step of applying said metal layer, including using said multi-layer structure as an implantation mask during said ion implantation.
Claim 5
Dependent Claim
94 words
A method as claimed in claim 1, wherein said multi-layer structure is produced by the steps of: producing a gate oxide layer on said substrate; applying a doped polysilicon layer onto said gate oxide layer; applying a diffusion barrier layer onto said doped polysilicon layer, said diffusion barrier layer being of a material of said diffusion barrier structure; depositing a silicon cover layer onto said diffusion barrier layer; and following a photo technique, producing said multi-layer structure by anisotropic re-etching of said silicon cover layer, said diffusion barrier layer and said doped polysilicon layer.
Claim 6
Dependent Claim
39 words
A method as claimed in claim 4, wherein said diffusion barrier layer is of TiN and further comprising the step of: subjecting said diffusion barrier layer to a temperature treatment before said step of depositing said silicon cover layer.
Claim 7
Dependent Claim
35 words
A method as claimed in claim 1, wherein said step of producing spacers includes the steps of: producing a surface wide uniform insulating layer; and forming said spacers by anisotropic re-etching of said insulating layer.
Claim 8
Independent Claim
150 words
A method for producing a multi-layer gate electrode containing doped polysilicon and metal silicide in a MOS transistor, comprising the steps of: producing a multi-layer structure having side walls on a substrate provided with a gate oxide, said multi-layer structure being produced at a location prescribed for a multi-layer gate electrode, said multi-layer structure including a doped polysilicon structure on said substrate, a diffusion barrier structure on said doped polysilicon structure and a silicon structure on said diffusion barrier structure; producing spacers at said side walls of said multi-layer structure; applying a metal layer onto said substrate and said multi-layer structure; and producing a metal silicide structure from said metal layer and said silicon structure using a temperature treatment; wherein said diffusion barrier structure is of a material which prevents diffusion of dopant from said polysilicon structure into said metal silicide structure, said diffusion barrier structure being composed of TiN.
Claim 9
Independent Claim
150 words
A method for producing a multi-layer gate electrode containing doped polysilicon and metal silicide in a MOS transistor, comprising the steps of: producing a multi-layer structure having side walls on a substrate provided with a gate oxide, said multi-layer structure being produced at a location prescribed for a multi-layer gate electrode, said multi-layer structure including a doped polysilicon structure on said substrate, a diffusion barrier structure on said doped polysilicon structure and a silicon structure on said diffusion barrier structure; producing spacers at said side walls of said multi-layer structure; applying a metal layer onto said substrate and said multi-layer structure; and producing a metal silicide structure from said metal layer and said silicon structure using a temperature treatment; wherein said diffusion barrier structure is of a material which prevents diffusion of dopant from said polysilicon structure into said metal silicide structure, said diffusion barrier structure being composed of TiN.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1995-11-17 | 1996-05-18 | 1996-11-17 | $2000.00 | Window Closed / Lapsed |
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