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US4562640A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of manufacturing stable, low resistance contacts in integrated semiconductor circuits

Assignee: Siemens AG
•
Filing: 1984-03-22
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Granted: 1986-01-07
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Expires: 2004-03-22
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Abstract

Abstract A method of manufacturing stable, low resistance contacts in an integrated semiconductor circuit which involves providing highly doped impurity diffused regions in a silicon substrate, forming a silicon dioxide layer over the highly doped diffused regions and the surrounding substrate, forming contact holes of uniform size in the silicon dioxide layer in selected areas of the highly doped diffused regions, applying a layer including a metal silicide into the holes in contact with the underlying highly doped diffused regions, applying an n + -doped polysilicon layer into the contact holes and over the silicon dioxide layer with a thickness corresponding to about half the contact hole side length, and then depositing a layer of predominantly aluminum over the n + -doped polysilicon layer.

Inventors

  • 👤 Dietrich Widmann
  • 👤 Reiner Sigusch

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 09:59
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10W20/40; H10W20/41; H10W20/44; H10W20/4451; Y; Y10; Y10S; Y10S148/00; Y10S148/019

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 168 words
A method of manufacturing stable, low resistance contacts in an integrated semiconductor circuit which comprises: providing highly doped diffused regions in a silicon substrate, forming a silicon dioxide layer over said highly doped diffused regions in the surrounding substrate, forming contact holes of uniform size in said silicon dioxide layer in selected areas of said highly doped diffused regions, said contact holes being matched to the minimum dimensions of the circuit elements, with a plurality of such uniform contact holes being provided in diffused regions of larger area, applying a layer including a metal silicide into said holes in contact with the underlying highly doped diffused region but insufficient to completely fill the contact holes, applying an n + -doped polysilicon layer into the contact holes and over the silicon dioxide layer, the thickness of said n + -doped layer above the contact holes being approximately one-half the length of a side of said contact holes, and depositing a layer of predominantly aluminum over the doped polysilicon layer.
Claim 2
Independent Claim 168 words
A method of manufacturing stable, low resistance contacts in an integrated semiconductor circuit which comprises: providing highly doped diffused regions in a silicon substrate, forming a silicon dioxide layer over said highly doped diffused regions in the surrounding substrate, forming contact holes of uniform size in said silicon dioxide layer in selected areas of said highly doped diffused regions, said contact holes being matched to the minimum dimensions of the circuit elements, with a plurality of such uniform contact holes being provided in diffused regions of larger area, applying a layer including a metal silicide into said holes in contact with the underlying highly doped diffused region but insufficient to completely fill the contact holes, applying an n + -doped polysilicon layer into the contact holes and over the silicon dioxide layer, the thickness of said n + -doped layer above the contact holes being approximately one-half the length of a side of said contact holes, and depositing a layer of predominantly aluminum over the doped polysilicon layer.
Claim 3
Dependent Claim 13 words
A method according to claim 1 wherein said metal silicide is platinum silicide.
Claim 4
Dependent Claim 16 words
A method according to claim 1 wherein said aluminum layer contains from 1 to 2% silicon.
Claim 5
Dependent Claim 22 words
A method according to claim 3 wherein copper in an amount of up to 6% is also present in said aluminum layer.
Claim 6
Dependent Claim 29 words
A method according to claim 1 wherein: said n + -doped polysilicon layer is deposited at substantially the same rate on horizontal and vertical portions of the substrate surface.
Claim 7
Dependent Claim 23 words
A method according to claim 5 wherein: said n + -doped polysilicon is deposited by means of a low pressure vapor phase deposition.
Claim 8
Dependent Claim 23 words
A method according to claim 5 wherein: said n + -doped polysilicon is deposited by means of a plasma induced vapor phase deposition.
Claim 9
Dependent Claim 23 words
A method according to claim 5 wherein: said n + -doped polysilicon is deposited by means of a photochemically induced vapor phase deposition.
Claim 10
Dependent Claim 25 words
A method according to claim 1 wherein the n + -doped polysilicon layer is back-etched so that only the contact holes remain filled with polysilicon.

References Cited (Backward Citations)

US4187599A Cited
US4141022A Cited
US4206472A Cited
US4233337A Cited
US4434544A Cited
US4424578A Cited
US4392150A Cited
US4361599A Cited
US4378628A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-01-06 1989-07-08 1990-01-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-01-06 1993-07-08 1994-01-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-01-06 1997-07-08 1998-01-07 $7700.00 Window Closed / Lapsed

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