Polysilicon-via structure for four transistor, triple polysilicon layer SRAM cell including two polysilicon layer load resistor

Claim 2

An SRAM transistor cell on a doped semiconductor substrate comprising: a first pass transistor and a second pass transistor, each having a source region, a drain region and a gate conductor formed from a first conductor layer, SAC structures composed of a second conductor layer forming connections to said source region and said drain region, and third conductor layer forming a load resistor and a butted contact to a said SAC structure to one of said source region and said drain region, a buried contact connected to said one of said source region and said drain region, a first pull-down transistor and a second pull-down transistor each having a source region, a drain region and a gate conductor, a first node and a second node, a first load resistor having one end connected to said first node and the other end thereof connected to said power supply connection, a second load resistor having one end connected to said second node and the other end thereof connected to said power supply connection, a bit line and a bit line bar, first and second interconnection lines, said first pull-down transistor having the drain region thereof connected to said first node, said second pull-down transistor having the drain region thereof connected to said second node, said first and second pull-down transistors having the source regions thereof connected together, said first node cross connected via said first interconnection line to the gate conductor of said second transistor, said second node cross connected via said second interconnection line to the gate conductor of said first transistor, said gate conductors of said first and second pass transistors connecting to a wordline, connection of said drain region of said first pass transistor to said first node, connection of said drain region of said second pass transistor to said second node, connection of said source region of said first pass transistor to said bit line bar and connection of said source region of said second pass transistor to said bit line.

Claim 3

An SRAM transistor cell on a doped semiconductor substrate comprising: buried contact areas in a well in said substrate, a first conductor layer on said well, a hard silicon oxide mask layer over said first conductor layer, gate conductors formed from said first conductor layer, lightly doped source/drain regions in said well, spacers in said well, source/drain regions in said well, a first inter-conductor dielectric layer on said cell, a self-aligned contact region in said cell above at least one of said source/drain regions, a second conductor layer over said cell patterned to form a via in said self-aligned contact region, a second inter-conductor dielectric layer on said cell, a third conductor layer over said cell patterned to form a first resistor connected to said self-aligned contact region.

Claim 4

An SRAM transistor cell on a doped semiconductor substrate comprising: buried contact areas in a well in said substrate, a first conductor layer on said well, a hard silicon oxide mask layer over said first conductor layer, gate conductors formed from said first conductor layer, lightly doped source/drain regions in said well, spacers in said well, source/drain regions in said well, a first inter-conductor dielectric layer on said cell, a self-aligned contact region in said cell above at least one of said source/drain regions, a second conductor layer over said cell patterned to form a via in said self-aligned contact region, a second inter-conductor dielectric layer on said cell, a third conductor layer over said cell patterned to form a first resistor connected to said self-aligned contact region.

Claim 5

A device in accordance with claim 2 including: said self-aligned contact regions to a said source region and a said drain region with an interconnection to said buried contact.

Claim 6

A device in accordance with claim 2 including: said first conductor layer comprising a layer selected from the group of polysilicon and polysilicon/polycide.

Claim 7

A device in accordance with claim 2 including: said second conductor layer comprising a lamination of polysilicon and tungsten silicide.

Claim 8

A device in accordance with claim 2 including: said hard silicon oxide mask layer being composed of a material formed from the group consisting of PETEOS and LPTEOS.

Claim 9

A device in accordance with claim 2 including: said first inter-conductor dielectric layer being composed of a material formed from the group consisting of LPTEOS and PETEOS.

Claim 10

A device in accordance with claim 2 including: said second inter-conductor dielectric layer being composed of a material formed from the group consisting of LPTEOS and PETEOS.

Claim 11

An SRAM transistor cell on a well in a semiconductor substrate comprises: a gate oxide layer over said well, a split polysilicon layer over said gate oxide layer, buried contact areas in a well in said substrate etching away portions of said split polysilicon layer and said gate oxide layer, buried contact regions in said well, a lower conductor layer selected from the group consisting of a polysilicon layer and a lamination of a polysilicon layer and a polycide layer, said lower conductor layer patterned into a gate conductor electrode, ion implanted LDD regions into said well adjacent to said gate conductor electrode, spacers adjacent to said gate conductor electrode, ion implanted source/drain regions self-aligned with said spacers adjacent to said gate conductor electrode, a first inter-conductor dielectric layer on said cell, a self-aligned contact region in said cell above at least one of said source/drain regions, a second conductor layer over said cell and patterned to form a via in said self-aligned contact region, a second inter-conductor dielectric layer on said cell, a third conductor layer over said cell and patterned to form a first resistor connected to said self-aligned contact region.

Claim 12

An SRAM transistor cell on a well in a semiconductor substrate comprises: a gate oxide layer over said well, a split polysilicon layer over said gate oxide layer, buried contact areas in a well in said substrate etching away portions of said split polysilicon layer and said gate oxide layer, buried contact regions in said well, a lower conductor layer selected from the group consisting of a polysilicon layer and a lamination of a polysilicon layer and a polycide layer, said lower conductor layer patterned into a gate conductor electrode, ion implanted LDD regions into said well adjacent to said gate conductor electrode, spacers adjacent to said gate conductor electrode, ion implanted source/drain regions self-aligned with said spacers adjacent to said gate conductor electrode, a first inter-conductor dielectric layer on said cell, a self-aligned contact region in said cell above at least one of said source/drain regions, a second conductor layer over said cell and patterned to form a via in said self-aligned contact region, a second inter-conductor dielectric layer on said cell, a third conductor layer over said cell and patterned to form a first resistor connected to said self-aligned contact region.

Claim 13

A device in accordance with claim 9 including: said self-aligned contact regions to a said source region and a said drain region with an interconnection to said buried contact.

Claim 14

A device in accordance with claim 9 including: said first conductor layer comprising a layer selected from the group of polysilicon and polysilicon/polycide.

Claim 15

A device in accordance with claim 9 including: said second conductor layer comprising a lamination of polysilicon and tungsten silicide.

Claim 16

A device in accordance with claim 9 including: said hard silicon oxide mask layer being composed of a material formed from the group consisting of PETEOS and LPTEOS.

Claim 17

A device in accordance with claim 9 including: said first inter-conductor dielectric layer being composed of a material formed from the group consisting of LPTEOS and PETEOS.

Claim 18

A device in accordance with claim 9 including: said second inter-conductor dielectric layer being composed of a material formed from the group consisting of LPTEOS and PETEOS.

Claim 19

An SRAM transistor cell on a doped semiconductor substrate comprises: a gate oxide layer over said substrate, a split polysilicon layer on said gate oxide layer, buried contact areas in a well in said substrate etching away portions of said split polysilicon layer and said gate oxide layer, a lower conductor layer selected from the group consisting of a polysilicon layer and a lamination of a polysilicon layer and a polycide layer over said split polysilicon layer and reaching down into contact with said substrate in said buried contact areas, a hard silicon oxide mask layer over said first conductor layer, defining gate conductors from said first conductor layer, lightly doped source/drain regions in said well, spacers in said well, source/drain regions in said well, a first inter-conductor dielectric layer on said cell, a self-aligned contact region defined in said cell above at least one of said source/drain regions, a second conductor layer over said cell and patterned to form a via in said self-aligned contact region, a second inter-conductor dielectric layer on said cell, a third conductor layer over said cell and patterned to form a first resistor connected to said self-aligned contact region, a first pass transistor and a second pass transistor, each having a source region, a drain region and a gate conductor, a first pull-down transistor and a second pull-down transistor each having a source region, a drain region and a gate conductor, a first node and a second node, a first load resistor having one end connected to said first node and the other end thereof connected to said power supply connection, a second load resistor having one end connected to said second node and the other end thereof connected to said power supply connection, a bit line and a bit line bar, first and second interconnection lines, said first pull-down transistor having the drain region thereof connected to said first node, said second pull-down transistor having the drain region thereof connected to said second node, said first and second pull-down transistors having the source regions thereof connected together, said first node cross connected via said first interconnection line to the gate conductor of said second transistor, said second node cross connected via said second interconnection line to the gate conductor of said first transistor, said gate conductors of said first and second pass transistors connecting to a wordline, connecting said drain region of said first pass transistor to said first node, connecting said drain region of said second pass transistor to said second node, connecting said source region of said first pass transistor to said bit line bar, and connecting said source region of said second pass transistor to said bit line.

Claim 20

An SRAM transistor cell on a doped semiconductor substrate comprises: a gate oxide layer over said substrate, a split polysilicon layer on said gate oxide layer, buried contact areas in a well in said substrate etching away portions of said split polysilicon layer and said gate oxide layer, a lower conductor layer selected from the group consisting of a polysilicon layer and a lamination of a polysilicon layer and a polycide layer over said split polysilicon layer and reaching down into contact with said substrate in said buried contact areas, a hard silicon oxide mask layer over said first conductor layer, defining gate conductors from said first conductor layer, lightly doped source/drain regions in said well, spacers in said well, source/drain regions in said well, a first inter-conductor dielectric layer on said cell, a self-aligned contact region defined in said cell above at least one of said source/drain regions, a second conductor layer over said cell and patterned to form a via in said self-aligned contact region, a second inter-conductor dielectric layer on said cell, a third conductor layer over said cell and patterned to form a first resistor connected to said self-aligned contact region, a first pass transistor and a second pass transistor, each having a source region, a drain region and a gate conductor, a first pull-down transistor and a second pull-down transistor each having a source region, a drain region and a gate conductor, a first node and a second node, a first load resistor having one end connected to said first node and the other end thereof connected to said power supply connection, a second load resistor having one end connected to said second node and the other end thereof connected to said power supply connection, a bit line and a bit line bar, first and second interconnection lines, said first pull-down transistor having the drain region thereof connected to said first node, said second pull-down transistor having the drain region thereof connected to said second node, said first and second pull-down transistors having the source regions thereof connected together, said first node cross connected via said first interconnection line to the gate conductor of said second transistor, said second node cross connected via said second interconnection line to the gate conductor of said first transistor, said gate conductors of said first and second pass transistors connecting to a wordline, connecting said drain region of said first pass transistor to said first node, connecting said drain region of said second pass transistor to said second node, connecting said source region of said first pass transistor to said bit line bar, and connecting said source region of said second pass transistor to said bit line.