US5712181A
Expired / Lapsed
US
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Method for the formation of polycide gate in semiconductor device
Assignee: SK Hynix Inc
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Filing: 1995-11-29
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Granted: 1998-01-27
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Expires: 2015-11-29
Abstract
Abstract A method for the formation of gate in a semiconductor device is disclosed. The method for the formation of gate in a semiconductor device, comprising the steps of: forming amorphous silicon and polysilicon over a gate insulating film atop a semiconductor substrate, in due order; implanting impurity ions into the polysilicon and carrying out heat treatment; and forming a layer of a refractory metal over the silicon and carrying out heat treatment, to form polycide. Capable of preventing the degradation which is attributed to the penetration of impurities and thermal instability when forming a P + polygate, the method contribute to the improvement in electrical properties.
Inventors
- 👤 Jeong Soo Byun
- 👤 Hyeong Joon Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:24
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01306; H10D64/01308; H10D64/0131; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
176 words
A method for fabricating a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a gate insulating film thereon; (b) forming an amorphous silicon layer about 2,500 angstroms thick on the gate insulating film; (c) forming a polysilicon layer on the amorphous silicon layer, the polysilicon layer being thinner than the amorphous silicon layer; (d) implanting impurity ions into the polysilicon layer such that a concentration of the impurity ions in the polysilicon layer is higher than a concentration of the impurity ions in the amorphous silicon layer, wherein the impurity ions are BF 2 ions; (e) after step (d), conducting heat treatment on the semiconductor device, thereby forming vertical grain boundaries in the amorphous silicon layer and forming vertical grain boundaries in the polysilicon layer, wherein the vertical grain boundaries formed in the amorphous silicon layer are not connected with the vertical grain boundaries formed in the polysilicon layer; and then (f) forming a refractory metal layer on the polysilicon layer and then annealing the refractory metal layer to form a polycide.
Claim 2
Independent Claim
176 words
A method for fabricating a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a gate insulating film thereon; (b) forming an amorphous silicon layer about 2,500 angstroms thick on the gate insulating film; (c) forming a polysilicon layer on the amorphous silicon layer, the polysilicon layer being thinner than the amorphous silicon layer; (d) implanting impurity ions into the polysilicon layer such that a concentration of the impurity ions in the polysilicon layer is higher than a concentration of the impurity ions in the amorphous silicon layer, wherein the impurity ions are BF 2 ions; (e) after step (d), conducting heat treatment on the semiconductor device, thereby forming vertical grain boundaries in the amorphous silicon layer and forming vertical grain boundaries in the polysilicon layer, wherein the vertical grain boundaries formed in the amorphous silicon layer are not connected with the vertical grain boundaries formed in the polysilicon layer; and then (f) forming a refractory metal layer on the polysilicon layer and then annealing the refractory metal layer to form a polycide.
Claim 3
Dependent Claim
28 words
The method of claim 1, wherein said annealing step forms the polycide on silicon of a gate electrode and the polycide reduces the resistance of the gate electrode.
Claim 4
Dependent Claim
28 words
The method of claim 1, wherein the polysilicon layer has a thickness such that the polysilicon layer is consumed when the polycide is formed during said annealing step.
Claim 5
Dependent Claim
15 words
The method of claim 1, wherein the metal of the refractory metal layer is cobalt.
Claim 6
Dependent Claim
24 words
The method of claim 1, wherein step (e) causes the implanted impurity ions to diffuse into the amorphous silicon layer and the polysilicon layer.
Claim 7
Dependent Claim
23 words
The method of claim 1, wherein the heat treatment of step (e) is done at about 900 degrees Celsius for about 70 minutes.
Claim 8
Dependent Claim
14 words
The method of claim 1, wherein the polysilicon layer is about 1,000 angstroms thick.
Claim 9
Dependent Claim
15 words
The method of claim 1, wherein the gate insulating film is about 80 angstroms thick.
References Cited (Backward Citations)
US4950617A
Cited
US5185279A
Cited
JPH0277161A
Cited
US4978629A
Cited
US5030584A
Cited
US5081066A
Cited
JPH04100219A
Cited
JPH04206934A
Cited
US5279976A
Cited
US5147820A
Cited
US5298436A
Cited
JPH05109986A
Cited
JPH05144730A
Cited
US5321286A
Cited
US5278096A
Cited
US5330929A
Cited
JPH06132523A
Cited
US5350698A
Cited
US5364803A
Cited
US5441904A
Cited
US5393682A
Cited
US5393687A
Cited
US5438006A
Cited
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-01-26 | 2001-07-28 | 2002-01-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-01-26 | 2005-07-28 | 2006-01-27 | $3760.00 | Window Closed / Lapsed |
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