Method of making tapered poly profile for TFT device manufacturing

Claim 1

The method of forming a thin film transistor integrated circuit with a tapered polysilicon profile comprising: depositing a layer of polysilicon over the surface of a semiconductor substrate; implanting ions into said polysilicon layer whereby the upper half of said polysilicon layer is damaged by the presence of said ions within said layer; anisotropically etching said polysilicon layer; isotropically etching said damaged portion of said polysilicon layer whereby said polysilicon layer is uniformly tapered; depositing a layer of gate oxide over the surface of said uniformly tapered polysilicon layer; forming a thin film transistor body comprising: depositing a layer of amorphous silicon over the surface of said gate oxide layer; covering said amorphous silicon layer overlying said uniformly tapered polysilicon layer with a photoresist mask wherein said covered portion of said amorphous silicon layer forms the channel of said thin film transistor body; and implanting ions into said amorphous silicon layer not covered by said photoresist mask to form source/drain regions within said amorphous silicon layer to complete formation of said thin film transistor body; depositing an insulating layer over said thin film transistor body and said semiconductor substrate; opening contacts through said insulating layer to said source/drain regions; and filling said contact openings with a conductive material to complete said contacts in the formation of said thin film transistor integrated circuit.

Claim 2

The method of forming a thin film transistor integrated circuit with a tapered polysilicon profile comprising: depositing a layer of polysilicon over the surface of a semiconductor substrate; implanting ions into said polysilicon layer whereby the upper half of said polysilicon layer is damaged by the presence of said ions within said layer; anisotropically etching said polysilicon layer; isotropically etching said damaged portion of said polysilicon layer whereby said polysilicon layer is uniformly tapered; depositing a layer of gate oxide over the surface of said uniformly tapered polysilicon layer; forming a thin film transistor body comprising: depositing a layer of amorphous silicon over the surface of said gate oxide layer; covering said amorphous silicon layer overlying said uniformly tapered polysilicon layer with a photoresist mask wherein said covered portion of said amorphous silicon layer forms the channel of said thin film transistor body; and implanting ions into said amorphous silicon layer not covered by said photoresist mask to form source/drain regions within said amorphous silicon layer to complete formation of said thin film transistor body; depositing an insulating layer over said thin film transistor body and said semiconductor substrate; opening contacts through said insulating layer to said source/drain regions; and filling said contact openings with a conductive material to complete said contacts in the formation of said thin film transistor integrated circuit.

Claim 4

The method of claim i wherein said ions implanted into said polysilicon layer are arsenic ions with a dosage of between about 1 E 15 to 3 E 15 atoms/cm 2 and energy of between about 10 to 30 KeV wherein said energy is adjusted so that the projected depth of said ions is within said upper half of said polysilicon layer.

Claim 12

The method of forming a thin film transistor integrated circuit with a tapered polysilicon profile comprising: depositing a layer of polysilicon over the surface of a semiconductor substrate; implanting ions into said polysilicon layer whereby the upper half of said polysilicon layer is damaged by the presence of said ions within said layer; anisotropically etching said polysilicon layer; isotropically etching said damaged portion of said polysilicon layer whereby said polysilicon layer is uniformly tapered; depositing a layer of gate oxide over the surface of said uniformly tapered polysilicon layer; forming a thin film transistor body overlying said gate oxide layer wherein said forming said thin film transistor body comprises the steps of: depositing a layer of amorphous silicon over the surface of said gate oxide layer; crystallizing said amorphous silicon layer to yield uniform grain sizes; covering said crystallized amorphous silicon layer overlying said uniformly tapered polysilicon layer with a photoresist mask wherein said covered portion of said crystallized amorphous silicon layer forms the channel of said thin film transistor body; and implanting ions into said crystallized amorphous silicon layer not covered by said photoresist mask to form source/drain regions within said amorphous silicon layer to complete formation of said thin film transistor body; depositing an insulating layer over said thin film transistor body and said semiconductor substrate; opening contacts through said insulating layer to source/drain regions within said thin film transistor body; and filling said contact openings with a conductive material to complete said contacts in the formation of said thin film transistor integrated circuit.

Claim 13

The method of forming a thin film transistor integrated circuit with a tapered polysilicon profile comprising: depositing a layer of polysilicon over the surface of a semiconductor substrate; implanting ions into said polysilicon layer whereby the upper half of said polysilicon layer is damaged by the presence of said ions within said layer; anisotropically etching said polysilicon layer; isotropically etching said damaged portion of said polysilicon layer whereby said polysilicon layer is uniformly tapered; depositing a layer of gate oxide over the surface of said uniformly tapered polysilicon layer; forming a thin film transistor body overlying said gate oxide layer wherein said forming said thin film transistor body comprises the steps of: depositing a layer of amorphous silicon over the surface of said gate oxide layer; crystallizing said amorphous silicon layer to yield uniform grain sizes; covering said crystallized amorphous silicon layer overlying said uniformly tapered polysilicon layer with a photoresist mask wherein said covered portion of said crystallized amorphous silicon layer forms the channel of said thin film transistor body; and implanting ions into said crystallized amorphous silicon layer not covered by said photoresist mask to form source/drain regions within said amorphous silicon layer to complete formation of said thin film transistor body; depositing an insulating layer over said thin film transistor body and said semiconductor substrate; opening contacts through said insulating layer to source/drain regions within said thin film transistor body; and filling said contact openings with a conductive material to complete said contacts in the formation of said thin film transistor integrated circuit.