Interconnecting layer on a semiconductor substrate

Claim 1

A semiconductor arrangement in which a plurality of field effect transistors are formed as an array on a semiconductor substrate, and at least one elongate power supply rail is formed on said semiconductor substrate so as to extend adjacent said array of transistors, comprising: a semiconductor substrate which is doped to be of a given conductivity type; a plurality of first regions in said substrate which are doped to be of opposite conductivity type to said given conductivity type to form respective source regions of said plurality of field effect transistors; a plurality of second regions in said substrate which are doped to be of said opposite conductivity type to form respective drain regions of said plurality of field effect transistors; an elongate third region in said substrate of which at least parts are heavily doped to be of said given conductivity type, which third region defines the extent of said at least one elongate power supply rail; said first, second and third regions extending into said semiconductor substrate from a surface thereof; each of said first, second and third regions being provided at said surface with a respective layer of tungsten deposited on said surface of said semiconductor substrate, the layer of tungsten over said third region constituting said at least one elongate power supply rail; an electrically insulating layer formed over said layers of tungsten, said insulating layer having provided therein a plurality of apertures through which at least one electrical connection may be made to each of said respective layers of tungsten; and at least one electrically conductive interconnecting layer formed over said insulating layer between two of said apertures so as electrically to interconnect the respective layers of tungsten of a region of a respective one of said transistors and said power supply rail.