US4628340A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS RAM with no latch-up phenomenon
Assignee: Toshiba Corp
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Filing: 1983-02-22
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Granted: 1986-12-09
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Expires: 2003-02-22
Abstract
Abstract A complementary-symmetry metal-oxide semiconductor device is made of a semiconductor substrate of a first conductivity type and well regions of a second conductivity type formed in the surface region of the semiconductor substrate. The well regions consist of a first well region and a second well region having a lower resistance per unit area than the first well region. An input-output peripheral circuit is formed of the second well region and the substrate. An internal circuit is formed of the first well region and the substrate.
Inventors
- 👤 Kazuhiko Hashimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 23:47
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
161 words
A complementary-symmetry MOS RAM-type semiconductor device for use in applications having peripheral systems, the device having a circuit for interacting with the peripheral systems as well as a circuit to provide the RAM function, the device comprising: a semiconductor substrate of a first conductivity type; a first well region of a second conductivity type which is formed in the surface region of said substrate; a second well region of a second conductivity type which is formed in the surface region of said substrate with a smaller resistance per unit area than said first well region; a first complementary-symmetry MOS circuit formed of said first well region and substrate; and a second complementary-symmetry MOS circuit formed of said second well region and substrate, wherein said first complementary-symmetry MOS circuit constitutes the RAM function circuit and said second complementary-symmetry MOS circuit constitutes the peripheral systems interaction circuit, for suppressing the occurrence of latch-up without decreasing the degree of integration of said semiconductor device.
Claim 2
Dependent Claim
161 words
A complementary-symmetry MOS RAM-type semiconductor device for use in applications having peripheral systems, the device having a circuit for interacting with the peripheral systems as well as a circuit to provide the RAM function, the device comprising: a semiconductor substrate of a first conductivity type; a first well region of a second conductivity type which is formed in the surface region of said substrate; a second well region of a second conductivity type which is formed in the surface region of said substrate with a smaller resistance per unit area than said first well region; a first complementary-symmetry MOS circuit formed of said first well region and substrate; and a second complementary-symmetry MOS circuit formed of said second well region and substrate, wherein said first complementary-symmetry MOS circuit constitutes the RAM function circuit and said second complementary-symmetry MOS circuit constitutes the peripheral systems interaction circuit, for suppressing the occurrence of latch-up without decreasing the degree of integration of said semiconductor device.
Claim 3
Dependent Claim
39 words
A semiconductor device according to claim 1, wherein said first and second well regions are doped with an impurity at the same concentration, and said second well region is formed with a greater depth than said first well region.
Claim 4
Dependent Claim
37 words
A semiconductor device according to claim 1, wherein said first and second well regions have the same depth, and said second well region is doped with an impurity at a higher concentration than said first well region.
Claim 5
Dependent Claim
33 words
A semiconductor device according to claim 2, wherein said second well region has a depth of 3 to 10 μm, and said first well region is made shallower than said second well region.
Claim 6
Dependent Claim
48 words
A semiconductor device according to claim 3, wherein said second well region is doped with an impurity at a concentration of 5×10 15 to 8×10 16 /cm 3 , and said first well region is doped with an impurity at a lower concentration than said second well region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-08 | 1990-06-09 | 1990-12-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-08 | 1994-06-09 | 1994-12-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-08 | 1998-06-09 | 1998-12-09 | $7700.00 | Window Closed / Lapsed |